# Sudeb Dasgupta

Orcid: 0000-0002-4044-1594
According to our database

Collaborative distances:

^{1}, Sudeb Dasgupta authored at least 79 papers between 2006 and 2024.Collaborative distances:

## Timeline

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Book In proceedings Article PhD thesis Dataset Other## Links

#### On csauthors.net:

## Bibliography

2024

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture.

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network.

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology.

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network.

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Interface Trap Analysis in Multi-Fin FinFET Technology: a Crucial Reliability Issue in Digital Application.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN.

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations.

Microelectron. J., December, 2023

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm.

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology.

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.

Proceedings of the 19th International Conference on Synthesis, 2023

ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications.

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFET.

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime.

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application.

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

IEEE Trans. Circuits Syst. II Express Briefs, 2022

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications.

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet.

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective.

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI.

Proceedings of the IEEE International Reliability Physics Symposium, 2022

A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture.

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021

Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization.

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm.

Proceedings of the International Conference on Microelectronics, 2021

2020

Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals.

IEEE Trans. Circuits Syst., 2020

2018

J. Low Power Electron., 2018

2016

Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET.

Microelectron. J., 2016

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases.

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

Microelectron. J., 2015

Microelectron. J., 2015

Proceedings of the 28th International Conference on VLSI Design, 2015

Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies.

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Efficient static D-latch standard cell characterization using a novel setup time model.

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design.

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013

The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design.

Microelectron. Reliab., 2013

The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices.

Microelectron. Reliab., 2013

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field.

Microelectron. J., 2013

A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-T<sub>ox </sub>in CMOS VLSI Circuits.

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-<i>k</i> Spacers.

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations.

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2012

Microelectron. J., 2012

J. Circuits Syst. Comput., 2012

Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients.

IET Circuits Devices Syst., 2012

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance.

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance.

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues.

Proceedings of the International Symposium on Electronic System Design, 2012

2011

Microelectron. Reliab., 2011

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlN<sub>x</sub>) symmetric double gate MOSFET.

Microelectron. J., 2011

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options.

Microelectron. J., 2011

Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation.

Microelectron. J., 2011

Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology.

J. Low Power Electron., 2011

Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact.

IET Circuits Devices Syst., 2011

Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach.

Proceedings of the International Conference on Soft Computing for Problem Solving (SocProS 2011) December 20-22, 2011, 2011

Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

Microelectron. Reliab., 2010

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic.

Microelectron. J., 2010

Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs.

J. Low Power Electron., 2010

Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control.

J. Low Power Electron., 2010

Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic.

IET Circuits Devices Syst., 2010

Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach.

Proceedings of the Fourth UKSim European Symposium on Computer Modeling and Simulation, 2010

2009

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications.

VLSI Design, 2009

Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study.

J. Low Power Electron., 2009

A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications.

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design.

J. Comput., 2008

2007

Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET.

Microelectron. J., 2006