Sverre Wichlund

According to our database1, Sverre Wichlund authored at least 6 papers between 1998 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2008
Scan Test Response Compaction Combined with Diagnosis Capabilities.
J. Electron. Test., 2008

2006
Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Achieving design closure in a typical mixed-signal ASIC; a Design-For-Test centric approach.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2000
On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1998
On multilevel circuit partitioning.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998


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