Syuichi Miyaoka

According to our database1, Syuichi Miyaoka authored at least 2 papers between 2000 and 2001.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2001
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%.
IEEE J. Solid State Circuits, 2001

2000
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000


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