Eiji Yamasaki

According to our database, Eiji Yamasaki authored at least 4 papers between 1994 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2001

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%.

Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba

IEEE J. Solid State Circuits, 2001

2000

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%.

Yuji Yokoyama, Nybutaka Itoh, Masap Katayama, Kazumasa Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Tom Kobayashi, Syuichi Miyaoka, Nobuo Tamba

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1995

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.

Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda

IEEE J. Solid State Circuits, November, 1995

1994

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.

Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa

IEEE J. Solid State Circuits, April, 1994