T. Nandha Kumar

Orcid: 0000-0002-5033-3095

According to our database1, T. Nandha Kumar authored at least 36 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
An Inexact Newton Method For Unconstrained Total Variation-Based Image Denoising by Approximate Addition.
IEEE Trans. Emerg. Top. Comput., 2022

Mott Memristors and Neuronal Ion Channels: A Qualitative Analysis.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Approximate Computing in Image Compression and Denoising.
Proceedings of the Approximate Computing, 2022

2021
Commutative Approximate Adders: Analysis and Evaluation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Generic Expressions for Early Estimation of Performance of Binary Multipliers.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence in Engineering and Technology, 2021

2020
Analytical modelling of tantalum/titanium oxide-based multi-layer selector to eliminate sneak path current in RRAM arrays.
IET Circuits Devices Syst., 2020

2019
A Deterministic Low-Complexity Approximate (Multiplier-Less) Technique for DCT Computation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Electrical model of multi-level bipolar Ta<sub>2</sub>O<sub>5</sub>/TaO<sub>x</sub> Bi-layered ReRAM.
Microelectron. J., 2019

Approximate computing using frequency upscaling.
IET Circuits Devices Syst., 2019

2018
Approximate DCT Image Compression Using Inexact Computing.
IEEE Trans. Computers, 2018

Modeling of Current Conduction during RESET Phase of Pt/Ta2O5/TaOx/Pt Bipolar Resistive RAM Devices.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

Multifilamentary Conduction Modelling of Bipolar Ta2O5/TaOx Bi-Layered RRAM.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

2017
Phase change memory cell emulator circuit design.
Microelectron. J., 2017

Configurable memristive logic block for memristive-based FPGA architectures.
Integr., 2017

Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
A SPICE Model of the Ta<sub>2</sub>O<sub>5</sub>TaO<sub>x</sub> Bi-Layered RRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Implementation of time-aware sensing technique for multilevel phase change memory cell.
Microelectron. J., 2016

Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs.
Integr., 2016

Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays.
IET Circuits Devices Syst., 2016

Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT.
J. Electron. Test., 2016

Inexact designs for approximate low power addition by cell replacement.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Operational fault detection and monitoring of a memristor-based LUT.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Scalable Application-Dependent Diagnosisof Interconnects of SRAM-Based FPGAs.
IEEE Trans. Computers, 2014

A memristor-based LUT for FPGAs.
Proceedings of the 9th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2014

Lyapunov method for unperturbed double integrator systems.
Proceedings of the 13th International Conference on Control Automation Robotics & Vision, 2014

A Lyapunov method analysis for double integrator with bounded perturbation.
Proceedings of the 13th International Conference on Control Automation Robotics & Vision, 2014

A novel design of a memristor-based look-up table (LUT) for FPGA.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Multilevel phase change memory cell model.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
A Novel Heuristic Method for Application-Dependent Testing of a SRAM-Based FPGA Interconnect.
IEEE Trans. Computers, 2013

Fine grain faults diagnosis of FPGA interconnect.
Microprocess. Microsystems, 2013

Single-configuration fault detection in applicationdependent testing of field programmable gate array interconnects.
IET Comput. Digit. Tech., 2013

On the improved implementations of pre calculated sums of partial products based 7-bit unsigned parallel squarer.
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

2012
Locating faults in application-dependent interconnects of SRAM based FPGAs.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

On the multiple fault detection of a nano crossbar.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2008
An automated approach for locating multiple faulty LUTs in an FPGA.
Microelectron. Reliab., 2008


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