Fabrizio Lombardi

According to our database1, Fabrizio Lombardi authored at least 467 papers between 1984 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2009, "For contributions to testing and fault tolerance of digital systems".

Timeline

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Online presence:

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Bibliography

2020
Error-Tolerant Computation for Voting Classifiers With Multiple Classes.
IEEE Trans. Veh. Technol., 2020

Codes for Limited Magnitude Error Correction in Multilevel Cell Memories.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Approximate Computing: From Circuits to Applications [Scanning the Issue].
Proc. IEEE, 2020

A Retrospective and Prospective View of Approximate Computing [Point of View}.
Proc. IEEE, 2020

Scanning the Issue.
Proc. IEEE, 2020

Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities.
Proc. IEEE, 2020

Scheme for periodical concurrent fault detection in parallel CRC circuits.
IET Comput. Digit. Tech., 2020

2019
An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2019

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security.
ACM Trans. Embed. Comput. Syst., 2019

Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Deterministic Low-Complexity Approximate (Multiplier-Less) Technique for DCT Computation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes.
IEEE Trans. Computers, 2019

Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM).
IEEE Trans. Computers, 2019

Design and Analysis of Approximate Redundant Binary Multipliers.
IEEE Trans. Computers, 2019

Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation.
IEEE Trans. Computers, 2019

Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC).
IEEE Trans. Computers, 2019

Non-equilibrium critical dynamics of bursts in θ and δ rhythms as fundamental characteristic of sleep and wake micro-architecture.
PLoS Comput. Biol., 2019

Approximate computing using frequency upscaling.
IET Circuits Devices Syst., 2019

Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Approximate Arithmetic Circuits: Design and Evaluation.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications.
J. Signal Process. Syst., 2018

Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders.
J. Signal Process. Syst., 2018

On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Design, Evaluation and Application of Approximate High-Radix Dividers.
IEEE Trans. Multi Scale Comput. Syst., 2018

Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits.
IEEE Trans. Computers, 2018

A Stochastic Computational Multi-Layer Perceptron with Backward Propagation.
IEEE Trans. Computers, 2018

Approximate DCT Image Compression Using Inexact Computing.
IEEE Trans. Computers, 2018

An Energy-Efficient Online-Learning Stochastic Computational Deep Belief Network.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A Probabilistic Error Model and Framework for Approximate Booth Multipliers.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design of Majority Logic (ML) Based Approximate Full Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design of Approximate FFT with Bit-width Selection Algorithms.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Application of an Approximate 2-D Convolver with Error Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Design of Dynamic Range Approximate Logarithmic Multipliers.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Multiple Fault Detection in Nano Programmable Logic Arrays.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

An energy-efficient stochastic computational deep belief network.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Adaptive approximation in arithmetic circuits: A low-power unsigned divider design.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

2017
Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC).
IEEE Trans. Multi Scale Comput. Syst., 2017

Message from the Editor-in-Chief.
IEEE Trans. Emerg. Top. Comput., 2017

Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.
IEEE Trans. Computers, 2017

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing.
IEEE Trans. Computers, 2017

High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes.
IEEE Trans. Computers, 2017

Two Approximate Voting Schemes for Reliable Computing.
IEEE Trans. Computers, 2017

A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2017

Approximate reliability of multi-state two-terminal networks by stochastic analysis.
IET Networks, 2017

AOI-based data-centric circuits for near-memory processing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Design and operational assessment of an intra-cell hybrid L2 cache.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Partially universal modules for high performance logic circuit design.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

XOR gate based low-cost configurable RO PUF.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design of majority logic based approximate arithmetic circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design of Approximate Logarithmic Multipliers.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Logic-in-Memory With a Nonvolatile Programmable Metallization Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Welcome.
IEEE Trans. Sustain. Comput., 2016

Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation.
IEEE Trans. Reliab., 2016

A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems.
IEEE Trans. Multi Scale Comput. Syst., 2016

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.
IEEE Trans. Computers, 2016

Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems.
IEEE Trans. Computers, 2016

Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems.
IEEE Trans. Computers, 2016

Design and Analysis of Inexact Floating-Point Adders.
IEEE Trans. Computers, 2016

Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation.
IEEE Trans. Computers, 2016

A Modified Partial Product Generator for Redundant Binary Multipliers.
IEEE Trans. Computers, 2016

On the Design of Approximate Restoring Dividers for Error-Tolerant Applications.
IEEE Trans. Computers, 2016

Reliability and Criticality Analysis of Communication Networks by Stochastic Computation.
IEEE Netw., 2016

Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs.
Integr., 2016

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction.
Integr., 2016

Design and process variation analysis of CNTFET-based ternary memory cells.
Integr., 2016

Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays.
IET Circuits Devices Syst., 2016

Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT.
J. Electron. Test., 2016

IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices.
IEEE Access, 2016

A comparative evaluation of approximate multipliers.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A fully parallel approximate CORDIC design.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design of approximate Redundant Binary multipliers.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design and Performance Evaluation of Approximate Floating-Point Multipliers.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Adaptive Filter Design Using Stochastic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design and evaluation of an approximate Wallace-Booth multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Low-cost configurable ring oscillator PUF with improved uniqueness.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Design and analysis of an approximate 2D convolver.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Inexact designs for approximate low power addition by cell replacement.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015
A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells.
IEEE Trans. Very Large Scale Integr. Syst., 2015

On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures.
IEEE Trans. Reliab., 2015

Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory.
IEEE Trans. Multi Scale Comput. Syst., 2015

Parallel Decodable Two-Level Unequal Burst Error Correcting Codes.
IEEE Trans. Computers, 2015

Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM).
IEEE Trans. Computers, 2015

Design and Analysis of Approximate Compressors for Multiplication.
IEEE Trans. Computers, 2015

An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders.
IEEE Trans. Computers, 2015

A Design Approach for Compressor Based Approximate Multipliers.
Proceedings of the 28th International Conference on VLSI Design, 2015

Transmission gate-based approximate adders for inexact computing.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Matrix multiplication by an inexact systolic array.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM).
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A Comparative Review and Evaluation of Approximate Adders.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Approximate compressors for error-resilient multiplier design.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Evaluating the impact of spike and flicker noise in phase change memories.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Operational fault detection and monitoring of a memristor-based LUT.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An approximate voting scheme for reliable computing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Eic Message.
IEEE Trans. Emerg. Top. Comput., 2014

A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation.
IEEE Trans. Computers, 2014

Scalable Application-Dependent Diagnosisof Interconnects of SRAM-Based FPGAs.
IEEE Trans. Computers, 2014

Robust HSPICE modeling of a single electron turnstile.
Microelectron. J., 2014

HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

A memristor-based TCAM (Ternary Content Addressable Memory) cell.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

FDSOI SRAM cells for low power design at 22nm technology node.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

New 4T-based DRAM cell designs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A system-level scheme for resistance drift tolerance of a multilevel phase change memory.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A low-power, high-performance approximate multiplier with configurable partial error recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A hybrid non-volatile SRAM cell with concurrent SEU detection and correction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A novel design of a memristor-based look-up table (LUT) for FPGA.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
New Metrics for the Reliability of Approximate and Probabilistic Adders.
IEEE Trans. Computers, 2013

Analysis of Error Masking and Restoring Properties of Sequential Circuits.
IEEE Trans. Computers, 2013

A Novel Heuristic Method for Application-Dependent Testing of a SRAM-Based FPGA Interconnect.
IEEE Trans. Computers, 2013

Single-configuration fault detection in applicationdependent testing of field programmable gate array interconnects.
IET Comput. Digit. Tech., 2013

On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment.
J. Electron. Test., 2013

Effects of Poisson noise in a IF model with STDP and spontaneous replay of periodic spatiotemporal patterns, in absence of cue stimulation.
Biosyst., 2013

Extending Non-Volatile Operation to DRAM Cells.
IEEE Access, 2013

A PCM-based TCAM cell using NDR.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

A novel and improved design of a ternary CNTFET-based cell.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A novel scheme for concurrent error detection of OLS parallel decoders.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Cell design and comparative evaluation of a novel 1T memristor-based memory.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

A novel write-scheme for data integrity in memristor-based crossbar memories.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Macromodeling a phase change memory (PCM) cell by HSPICE.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

A novel sort error hardened 10T SRAM cells for low voltage operation.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Soft error masking latch for sub-threshold voltage operation.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Locating faults in application-dependent interconnects of SRAM based FPGAs.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Modeling a single electron turnstile in HSPICE.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A memristor-based TCAM (ternary content addressable memory) cell: design and evaluation.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Faults affecting the control blocks of PV arrays and techniques for their concurrent detection.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

On the design of two single event tolerant slave latches for scan delay testing.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

On the multiple fault detection of a nano crossbar.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Hardening a memory cell for low power operation by gate leakage reduction.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Editorial.
IEEE Trans. Computers, 2011

A hybrid memory cell using Single-Electron transfer.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A memristor-based memory cell using ambipolar operation.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Templated-Based Asynchronous Design for Testable and Fail-Safe Operation.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

On the Reliable Performance of Sequential Adders for Soft Computing.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

On the Delay Analysis of Defective CNTFETs with Undeposited CNTs.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Multiple Error Detection in DNA Self-Assembly Using Coded Tiles.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

State of the Journal.
IEEE Trans. Computers, 2010

An information-theoretic analysis of quantum-dot cellular automata for defect tolerance.
ACM J. Emerg. Technol. Comput. Syst., 2010

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability.
Integr., 2010

High throughput and low power dissipation in QCA pipelines using Bennett clocking.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Read-out schemes for a CNTFET-based crossbar memory.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

8Gb/s capacitive low power and high speed 4-PWAM transceiver design.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Time/Temperature Degradation of Solar Cells under the Single Diode Model.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Modeling Open Defects in Nanometric Scale CMOS.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Modelling a CNTFET with Undeposited CNT Defects.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

An Analytical Error Model for Pattern Clipping in DNA Self-Assembly.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
Introduction to the Special Section on Nanocircuits and Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates.
IEEE Trans. Instrum. Meas., 2009

On the Computational Complexity of Tile Set Synthesis for DNA Self-Assembly.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A defect/error-tolerant nanosystem architecture for DSP.
ACM J. Emerg. Technol. Comput. Syst., 2009

Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates.
J. Electron. Test., 2009

Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.
J. Electron. Test., 2009

Healing DNA Self-Assemblies Using Punctures.
J. Electron. Test., 2009

An Efficient Framework for Scalable Defect Isolation in Large Scale Networks of DNA Self-Assembly.
J. Electron. Test., 2009

Soft-Error Hardening Designs of Nanoscale CMOS Latches.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A coding framework for DNA self-assembly.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Errors in DNA Self-Assembly by Synthesized Tile Sets.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

A Novel Hardened Design of a CMOS Memory Cell at 32nm.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Coded DNA Self-Assembly for Error Detection/Location.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Evaluation and Analysis of Heuristic Techniques for Vector Ordering of VLSI Test Sets.
IEEE Trans. Instrum. Meas., 2008

Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels.
IEEE Trans. Ind. Informatics, 2008

Two-Dimensional Schemes for Clocking/Timing of QCA Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Synthesis of Tile Sets for DNA Self-Assembly.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Serial Memory by Quantum-Dot Cellular Automata (QCA).
IEEE Trans. Computers, 2008

A Selective Trigger Scan Architecture for VLSI Testing.
IEEE Trans. Computers, 2008

A model for computing and energy dissipation of molecular QCA devices and circuits.
ACM J. Emerg. Technol. Comput. Syst., 2008

Analysis and Evaluations of Reliability of Reconfigurable FPGAs.
J. Electron. Test., 2008

Substrate Testing on a Multi-Site/Multi-Probe ATE.
J. Electron. Test., 2008

Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA.
J. Electron. Test., 2008

Monomer Control for Error Tolerance in DNA Self-Assembly.
J. Electron. Test., 2008

Device Model for Ballistic CNFETs Using the First Conducting Band.
IEEE Des. Test Comput., 2008

A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-Assemblies.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Low power 8T SRAM using 32nm independent gate FinFET technology.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Design of defect tolerant tile-based QCA circuits.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A low leakage 9t sram cell for ultra-low power operation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Fault Tolerant Schemes for QCA Systems.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

A Tile-Based Error Model for Forward Growth of DNA Self-Assembly.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Checkpointing of Rectilinear Growth in DNA Self-Assembly.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Error Detection/Correction in DNA Algorithmic Self-Assembly.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Cost-Driven Optimization of Coverage of Combined Built-In Self-Test/Automated Test Equipment Testing.
IEEE Trans. Instrum. Meas., 2007

An Integrated Environment for Design Verification of ATE Systems.
IEEE Trans. Instrum. Meas., 2007

Editor's Note.
IEEE Trans. Computers, 2007

Introduction to the Special Section on Nano Systems and Computing.
IEEE Trans. Computers, 2007

Design of sequential circuits by quantum-dot cellular automata.
Microelectron. J., 2007

Analysis of missing and additional cell defects in sequential quantum-dot cellular automata.
Integr., 2007

Low overhead DFT using CDFG by modifying controller.
IET Comput. Digit. Tech., 2007

On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire.
J. Electron. Test., 2007

QCA Circuits for Robust Coplanar Crossing.
J. Electron. Test., 2007

Guest Editors' Introduction: The State of the Art in Nanoscale CAD.
IEEE Des. Test Comput., 2007

An Overview of Nanoscale Devices and Circuits.
IEEE Des. Test Comput., 2007

Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Robust self-assembly of interconnects by parallel DNA growth.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Modeling facet roughening errors in self-assembly by snake tile sets.
Proceedings of the 2007 IEEE International Test Conference, 2007

RT level reliability enhancement by constructing dynamic TMRS.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Testing Reversible One-Dimensional QCA Arrays for Multiple Faults.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Error Tolerance of DNA Self-Healing Assemblies by Puncturing.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Error rate reduction in DNA self-assembly by non-constant monomer concentrations and profiling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Measuring the timing jitter of ATE in the frequency domain.
IEEE Trans. Instrum. Meas., 2006

Evaluating the Yield of Repairable SRAMs for ATE.
IEEE Trans. Instrum. Meas., 2006

Agencies for perception in environmental monitoring.
IEEE Trans. Instrum. Meas., 2006

Editors' Note.
IEEE Trans. Computers, 2006

Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC).
IEEE Trans. Computers, 2006

HDLQ: A HDL environment for QCA design.
ACM J. Emerg. Technol. Comput. Syst., 2006

Connecting and Configuring Defective Nano-Scale Networks for DNA Self-Assembly.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Reliability Evaluation of Repairable/Reconfigurable FPGAs.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Multi-Site and Multi-Probe Substrate Testing on an ATE.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Testing Reversible 1D Arrays for Molecular QCA.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Error Tolerance of DNA Self-Assembly by Monomer Concentration Control.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A Novel Methodology for Functional Test Data Compression.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Defect tolerance of QCA tiles.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Novel designs for thermally robust coplanar crossing in QCA.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Environmental-based characterization of SoC-based instrumentation systems for stratified testing.
IEEE Trans. Instrum. Meas., 2005

Evaluation, analysis, and enhancement of error resilience for reliable compression of VLSI test data.
IEEE Trans. Instrum. Meas., 2005

Analysis and evaluation of multisite testing for VLSI.
IEEE Trans. Instrum. Meas., 2005

Reliability measurement of mass storage system for onboard instrumentation.
IEEE Trans. Instrum. Meas., 2005

Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Editor's Note.
IEEE Trans. Computers, 2005

Application of Arithmetic Coding to Compression of VLSI Test Data.
IEEE Trans. Computers, 2005

Tile-based QCA design using majority-like logic primitives.
ACM J. Emerg. Technol. Comput. Syst., 2005

A probabilistic analysis of fault tolerance for switch block array in FPGAs.
Int. J. Embed. Syst., 2005

A Comparative Evaluation of Designs for Reliable Memory Systems.
J. Electron. Test., 2005

Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale.
IEEE Des. Test Comput., 2005

A Flow Graph Technique for DFT Controller Modification.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Improving Error Resilience for Compressed Test Sets by Don't Care Assignment.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Design of a QCA Memory with Parallel Read/Serial Write.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Evaluating the Data Integrity of Memory Systems by Configurable Markov Models.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Tile-based design of a serial memory in QCA.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Enhancing error resilience for reliable compression of VLSI test data.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Two dimensional reordering of functional test data for compression by ATE.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Modeling QCA Defects at Molecular-level in Combinational Circuits.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Defect Characterization and Tolerance of QCA Sequential Devices and Circuits.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Data Dependent Jitter (DDJ) Characterization Methodology.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Modeling and Analysis of Jitter in ATE Using Matlab.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories.
Proceedings of the 2005 Design, 2005

Evaluation of Error-Resilience for Reliable Compression of Test Data.
Proceedings of the 2005 Design, 2005

2004
Sequential diagnosis of processor array systems.
IEEE Trans. Reliab., 2004

Using data compression in automatic test equipment for system-on-chip testing.
IEEE Trans. Instrum. Meas., 2004

Analysis and measurement of fault coverage in a combined ATE and BIST environment.
IEEE Trans. Instrum. Meas., 2004

Evaluating the repair of system-on-chip (SoC) using connectivity.
IEEE Trans. Instrum. Meas., 2004

Testing Layered Interconnection Networks.
IEEE Trans. Computers, 2004

Balanced dual-stage repair for dependable embedded memory cores.
J. Syst. Archit., 2004

Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.
J. Electron. Test., 2004

Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates.
IEEE Des. Test Comput., 2004

Defects and Faults in Quantum Cellular Automata at Nano Scale.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Markov Models of Fault-Tolerant Memory Systems under SEU.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Routability and Fault Tolerance of FPGA Interconnect Architectures.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Quantum Cellular Automata: New Defects and Faults for New Devices.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Simulation of reconfigurable memory core yield.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Design and characterization of an and-or-inverter (AOI) gate for QCA implementation.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Evaluation of heuristic techniques for test vector ordering.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

On The Yield of Compiler-Based eSRAMs.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Defect Characterization for Scaling of QCA Devices.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Error-Resilient Test Data Compression Using Tunstall Codes.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Compression of VLSI Test Data by Arithmetic Coding.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Reliability Modeling and Assurance of Clockless Wave Pipeline.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Scan Test of IP Cores in an ATE Environment.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Testing of Quantum Dot Cellular Automata Based Designs.
Proceedings of the 2004 Design, 2004

Fault Tolerance of Programmable Switch Blocks.
Proceedings of the 2004 Design, 2004

Fault tolerant clockless wave pipeline design.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Maximal diagnosis of interconnects of random access memories.
IEEE Trans. Reliab., 2003

Guest Editorial.
IEEE Trans. Instrum. Meas., 2003

Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment.
IEEE Trans. Instrum. Meas., 2003

Modeling and analysis of fault tolerant multistage interconnection networks.
IEEE Trans. Instrum. Meas., 2003

Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects.
IEEE Trans. Computers, 2003

Parallel testing of multi-port static random access memories.
Microelectron. J., 2003

Guest Editors' Introduction: Clockless VLSI Systems.
IEEE Des. Test Comput., 2003

Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.
Proceedings of the 2nd IEEE International Symposium on Network Computing and Applications (NCA 2003), 2003

Optimal Spare Utilization in Repairable and Reliable Memory Cores.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Hybrid Multisite Testing at Manufacturing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Yield Analysis of Compiler-Based Arrays of Embedded SRAMs.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

On the Test and Diagnosis of the Perfect Shuffle.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

ATE-Amenable Test Data Compression with No Cyclic Scan.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.
Proceedings of the International Conference on Embedded Systems and Applications, 2003

The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Analysis of stratified testing for multichip module systems.
IEEE Trans. Reliab., 2002

Quality enhancement of reconfigurable multichip module systems by redundancy utilization.
IEEE Trans. Instrum. Meas., 2002

Guest Editors' Introduction.
IEEE Trans. Computers, 2002

Quality-effective repair of multichip module systems.
J. Syst. Archit., 2002

Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems.
IEEE Des. Test Comput., 2002

Hardware/Software Co-Reliability of Configurable Digital Systems.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Random Testing of Multi-Port Static Random Access Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

A Scan-Bist Environment for Testing Embedded Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Testing Layered Interconnection Networks.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Data Compression for System-on-Chip Testing Using ATE.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Repairability Evaluation of Embedded Multiple Region DRAMs.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Testing and evaluating the quality-level of stratified multichip module instrumentation.
IEEE Trans. Instrum. Meas., 2001

Introduction to the Special Section on High Performance Memory Systems.
IEEE Trans. Computers, 2001

Fault Detection in a Tristate System Environment.
IEEE Micro, 2001

Guest Editors' Introduction: Fault-Tolerant Embedded Systems.
IEEE Micro, 2001

Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems.
IEEE Des. Test Comput., 2001

Modeling the Dependability of N-Modular Redundancy on Demand under Malicious Agreement.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Connectivity-Based Multichip Module Repair.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Dependability under Malicious Agreement in N-modular Redundancy-on-Demand Systems.
Proceedings of the IEEE International Symposium on Network Computing and Applications (NCA 2001), 2001

A Parallel Approach for Testing Multi-Port Static Random Access Memories.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

Parallel Testing of Multi-port Static Random Access Memories for BIST.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Testing and testable designs for one-time programmable FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Testing SRAM-Based Content Addressable Memories.
IEEE Trans. Computers, 2000

Guest Editors' Introduction.
IEEE Trans. Computers, 2000

An Approach for Detecting Multiple Faulty FPGA Logic Blocks.
IEEE Trans. Computers, 2000

Detection of Inter-Port Faults in Multi-Port Static RAMs.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping.
Proceedings of the Parallel and Distributed Processing, 2000

On the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Testing the Configurability of Dynamic FPGAs.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Testing programmable interconnect systems: an algorithmic approach.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Test generation and scheduling for layout-based detection of bridge faults in interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Fault-tolerant rank order filtering for image enhancement.
IEEE Trans. Consumer Electron., 1999

Reconfiguring one-time programmable FPGAs.
IEEE Micro, 1999

Adaptive Fault Detection and Diagnosis of RAM Interconnects.
J. Electron. Test., 1999

Guest Editors' Introduction: DRAM Architecture and Testing.
IEEE Des. Test Comput., 1999

Design Verification of FPGA Implementations.
IEEE Des. Test Comput., 1999

Maximal Diagnosis of Interconnects of Random Access Memories.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Novel Fault Tolerant Approach for SRAM-Based FPGAs.
Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

Interconnect Diagnosis of Bus-Connected Multi-RAM Systems.
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Two-Step Algorithms for Maximal Diagnosis of Wiring Interconnects.
Proceedings of the Digest of Papers: FTCS-29, 1999

Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Good Processor Identification in Two-Dimensional Grids.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Novel Control Pattern Generators for Interconnect Testing with Boundary Scan.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Diagnosing Single Faults for Interconnects in SRAM Based FPGAs.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Testing configurable LUT-based FPGA's.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Structural diagnosis of interconnects by coloring.
ACM Trans. Design Autom. Electr. Syst., 1998

IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.
IEEE Trans. Computers, 1998

Embedded Fault-Tolerant Systems.
IEEE Micro, 1998

Field-Programmable Gate Arrays.
IEEE Des. Test Comput., 1998

Fault Detection and Diagnosis of Interconnects of Random Access Memories.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Bridging Fault Detection in FPGA Interconnects Using <i>I<sub>DDQ</sub></i>.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

A New Method for Testing EEPLA's.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

On the Complexity of Sequential Testing in Configurable FPGAs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Artificial Neural Networks for Motion Emulation in Virtual Environments.
Proceedings of the Modelling and Motion Capture Techniques for Virtual Environments, 1998

A Diagnosis Method for Interconnects in SRAM Based FPGAs.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Fault Detection in a Tristate System Environment.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
On the Fault Coverage of Interconnect Diagnosis.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

An Efficient Multi-Way Algorithm for Balanced Partitioning of VLSI Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Using Virtual Links for Reliable Information Retrieval Across Point-to-Point Networks.
Proceedings of the Digest of Papers: FTCS-27, 1997

Multiple fault detection in logic resources of FPGAs.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Testing of programmable logic devices (PLD) with faulty resources.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
A Sweeping Line Approach to Interconnect Testing.
IEEE Trans. Computers, 1996

Adaptive System-Level Diagnosis for Hypercube Multiprocessors.
IEEE Trans. Computers, 1996

Graph Algorithms for Conformance Testing Using the Rural Chinese Postman Tour.
SIAM J. Discret. Math., 1996

FsmTest: Functional test generation for sequential circuits.
Integr., 1996

An approach for testing programmable/configurable field programmable gate arrays.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

On the diagnosis of programmable interconnect systems: Theory and application.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Conformance Testing of Time-Dependent Protocols.
Proceedings of the 2nd IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '96), 1996

Space Cutting Approaches for Repairing Memories.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

A coloring approach to the structural diagnosis of interconnects.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Diagnosing Programmable Interconnect Systems for FPGAs.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Modeling Quality Reduction of Multichip Module Systems due to Uneven Fault-Coverage and Imperfect Diagnosis.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Layout-driven detection of bridge faults in interconnects.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Diagnosis of interconnects using a structured walking-1 approach.
Integr., 1995

Diagnosis of interconnects and FPICs using a structured walking-1 approach.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Accurate communication models for task scheduling in multicomputers.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

Fault-tolerant sorting in SIMD hypercubes.
Proceedings of IPPS '95, 1995

Diagnosing Multiple Bridge Faults in Baseline Multistage Interconnection Networks.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

A Submesh Allocation Scheme for Mesh-Connected Multiprocessor Systems.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

A New Diagnosis Approach for Short Faults in Interconnects.
Proceedings of the Digest of Papers: FTCS-25, 1995

Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

An improved approach to fault tolerant rank order filtering on a SIMD mesh processor.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Repair algorithms for mirrored disk systems.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

A row-based FPGA for single and multiple stuck-at fault detection.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994
Generating non-standard random distributions for discrete event simulation systems.
Simul. Pract. Theory, 1994

A divide-and-conquer methodology for system-level diagnosis of processor arrays.
Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994

Detecting Latent Sector Faults in Modern SCSI Disks.
Proceedings of the MASCOTS '94, Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems, January 31, 1994

Matrix multiplication on the MasPar using distance insensitive communication schemes.
Proceedings of the International Symposium on Parallel Architectures, 1994

An Approach for UIO Generation for FSM Verification and Validation.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Rank Order Filtering on an Array With Faulty Processors.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Scheduling Policies for Fault Tolerance in a VLSI Processor.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

On Soft Switch Programming for Reconfigurable Array Systems.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements.
IEEE Trans. Very Large Scale Integr. Syst., 1993

Fault detection in TFCMOS/DFCMOS combinational gates.
Integr., 1993

On the testability of array structures for FFT computation.
J. Electron. Test., 1993

On the design for testability of sequential circuits.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

An Adaptive System-Level Diagnosis Approach for Hypercube Multiprocessors.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

On the Methods to Detect Sector Faults of a Disk Subsystem.
Proceedings of the MASCOTS '93, 1993

Emulating Reconfigurable Arrays for Image Processing Using the MasPar Architecture.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

An Adaptive System-Level Diagnosis Approach for Mesh Connected Multiprocessors.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

On the minimal test set for single fault location.
Proceedings of the European Design Automation Conference 1993, 1993

On the Reconfigurable Operation of Arrays with Defects for Image Processing.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Detection of Defective Media in Disks.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
Protocol conformance testing using multiple UIO sequences.
IEEE Trans. Commun., 1992

Evaluation and improvement of fault coverage of conformance testing by UIO sequences.
IEEE Trans. Commun., 1992

Detection and Location of Multiple Faults in Baseline Interconnection Networks.
IEEE Trans. Computers, 1992

A data path approach for testing microprocessors with a fault bound: the MC68000 case.
Microprocess. Microsystems, 1992

Constant testability of combinational cellular tree structures.
J. Electron. Test., 1992

Detection of multiple faults in CMOS circuits using a behavioral approach.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

On the Verification and Validation of Protocols with High Fault Coverage Using UIO Sequences.
Proceedings of the 11th Symposium on Reliable Distributed Systems, 1992

1991
Minimizing the cost of repairing WSI memories.
Integr., 1991

On a new approach for enhancing the fault coverage of conformance testing of protocols.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991

Protocol Conformance Testing by Discriminating UIO Sequences.
Proceedings of the Protocol Specification, 1991

1990
New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Fault Detection and Design Complextity in C-Testable VLSI Arrays.
IEEE Trans. Computers, 1990

On the Constant Diagnosability of Baseline Interconnection Networks.
IEEE Trans. Computers, 1990

Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection.
J. Electron. Test., 1990

Evaluation and improvement of fault coverage for verification and validation of protocols.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

On the testability of array structures for FFT computation.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and Pipeline Delays.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
Reconfiguration of VLSI arrays by covering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Functional testing and verification of array systems.
Microprocess. Microsystems, 1989

On a new class of C-testable systolic arrays.
Integr., 1989

Location and Identification for Single and Multiple Faults in Testable Redundant PLAs for Yield Enhancement.
Proceedings of the Proceedings International Test Conference 1989, 1989

Fault detection in a testable PLA with low overhead for production testing.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

On a tapered floating point system.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1988
An algorithm for functional reconfiguration of fixed-size arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

On an improved design approach for C-testable orthogonal iterative arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

On Functional Testing of Array Processors.
IEEE Trans. Computers, 1988

Reconfiguration of hexagonal arrays by diagonal deletion.
Integr., 1988

Analysis of Comparison-Based Diagnosable Systems Using Temporal Criteria.
Comput. J., 1988

New Approaches for the Reconfiguration of Two-Dimensional VLSI Arrays Using Time-Redundancy.
Proceedings of the 9th IEEE Real-Time Systems Symposium (RTSS '88), 1988

Approaches for the repair of VLSI/WSI RRAMs by row/column deletion.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987
On the Repair of Redundant RAM's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

An Architecture and an Interconnection Scheme for Time-Sliced Buses.
J. Parallel Distributed Comput., 1987

On a Novel Self-Test Approach to Digital Testing.
Comput. J., 1987

A Technique for Reconfiguring Two Dimensional VLSI Arrays.
Proceedings of the 8th IEEE Real-Time Systems Symposium (RTSS '87), 1987

1986
An Architecture and an Interconnection Scheme for Time-Sliced Buses in Real-Time Processing.
Proceedings of the 7th IEEE Real-Time Systems Symposium (RTSS '86), 1986

1985
On a Multiprocessor System with Dynamic Redundancy.
Proceedings of the 6th IEEE Real-Time Systems Symposium (RTSS '85), 1985

1984
Investigation and design of a controller of an asynchronous system for fault-tolerant aircraft control using hybrid voting techniques.
Softw. Microsystems, 1984


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