T. Nirmalraj

According to our database, T. Nirmalraj authored at least 4 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of four.

2023

Design of Low-Power 10-Transistor Full Adder Using GDI Technique for Energy-Efficient Arithmetic Applications.

T. Nirmalraj, S. K. Pandiyan, Rakesh Kumar Karan, R. Sivaraman, Rengarajan Amirtharajan

Circuits Syst. Signal Process., June, 2023

2021

An Efficient Design for Area-Efficient Truncated Adaptive Booth Multiplier for Signal Processing Applications.

S. Radhakrishnan, Rakesh Kumar Karn, T. Nirmalraj

J. Circuits Syst. Comput., 2021

Automatic diagnosis of single fault in interconnect testing of SRAM-based FPGA.

T. Nirmalraj, S. Radhakrishnan, S. K. Pandiyan

IET Comput. Digit. Tech., 2021

2019

An enhanced Gate Diffusion Input technique for low power applications.

S. Radhakrishnan, T. Nirmalraj, Rakesh Kumar Karn

Microelectron. J., 2019