Takashi Hirayama

According to our database, Takashi Hirayama authored at least 18 papers between 1996 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2023

Enumerating Empty and Surrounding Polygons.

Shunta Terui, Katsuhisa Yamanaka, Takashi Hirayama, Takashi Horiyama, Kazuhiro Kurita, Takeaki Uno

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., September, 2023

Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.

Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

2022

A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs.

Taishu Ito, Yusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama

IEICE Trans. Inf. Syst., 2022

2020

A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs.

Yusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama

Proceedings of the Frontiers in Algorithmics - 14th International Workshop, 2020

2019

Exact Exponential Algorithm for Distance-3 Independent Set Problem.

Katsuhisa Yamanaka, Shogo Kawaragi, Takashi Hirayama

IEICE Trans. Inf. Syst., 2019

2018

Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units.

Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2016

New Two-Qubit Gate Library with Entanglement.

Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2014

A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.

Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani

IEICE Trans. Inf. Syst., 2014

2011

A Testable Realization for Decimal Multipliers.

Takashi Hirayama, Yasuaki Nishitani, Seiji Kitamura

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2009

Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions.

Takashi Hirayama, Yasuaki Nishitani

J. Circuits Syst. Comput., 2009

Let's make a tennis game!: introduction to game programming.

Takashi Hirayama

Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2009

2006

Efficient Search Methods for Obtaining Exact Minimum AND-EXOR Expressions.

Takashi Hirayama, Yasuaki Nishitani

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation.

Takashi Hirayama, Masatoshi Takahashi, Yasuaki Nishitani

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2004

New Three-Level Boolean Expression Based on EXOR Gates.

Ryoji Ishikawa, Takashi Hirayama, Goro Koda, Kensuke Shimizu

IEICE Trans. Inf. Syst., 2004

2002

A Faster Algorithm of Minimizing AND-EXOR Expressions.

Takashi Hirayama, Yasuaki Nishitani, Toru Sato

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Pseudocube-based expressions to enhance testability.

Ryoji Ishikawa, Tomonori Igarashi, Takashi Hirayama, Kensuke Shimizu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

1999

Exor Decomposition with Common Variables and its Application to Multiple-Output Networks.

Ryoji Ishikawa, Goro Koda, Kensuke Shimizu, Takashi Hirayama

J. Circuits Syst. Comput., 1999

1996

A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions.

Takashi Hirayama, Yasuaki Nishitani

Syst. Comput. Jpn., 1996