Takashi Hirayama

According to our database1, Takashi Hirayama authored at least 20 papers between 1996 and 2024.

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Bibliography

2024
New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
IEICE Trans. Inf. Syst., 2024

An Improved Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
Proceedings of the 54th IEEE International Symposium on Multiple-Valued Logic, 2024

2023
Enumerating Empty and Surrounding Polygons.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., September, 2023

Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

2022
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs.
IEICE Trans. Inf. Syst., 2022

2020
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs.
Proceedings of the Frontiers in Algorithmics - 14th International Workshop, 2020

2019
Exact Exponential Algorithm for Distance-3 Independent Set Problem.
IEICE Trans. Inf. Syst., 2019

2018
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2016
New Two-Qubit Gate Library with Entanglement.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2014
A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
IEICE Trans. Inf. Syst., 2014

2011
A Testable Realization for Decimal Multipliers.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2009
Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions.
J. Circuits Syst. Comput., 2009

Let's make a tennis game!: introduction to game programming.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2009

2006
Efficient Search Methods for Obtaining Exact Minimum AND-EXOR Expressions.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2004
New Three-Level Boolean Expression Based on EXOR Gates.
IEICE Trans. Inf. Syst., 2004

2002
A Faster Algorithm of Minimizing AND-EXOR Expressions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Pseudocube-based expressions to enhance testability.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

1999
Exor Decomposition with Common Variables and its Application to Multiple-Output Networks.
J. Circuits Syst. Comput., 1999

1996
A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions.
Syst. Comput. Jpn., 1996


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