Tam-Anh Chu

According to our database1, Tam-Anh Chu authored at least 13 papers between 1986 and 1995.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

1995
Guest Editors' Introduction: More Practical Asynchronous Design.
IEEE Des. Test Comput., 1995

1994
Synthesis of hazard-free control circuits from asynchronous finite state machines specifications.
J. VLSI Signal Process., 1994

Guest Editor's Introduction: Practical Asynchronous Design.
IEEE Des. Test Comput., 1994

1993
CLASS: a CAD system for automatic synthesis and verification of asynchronous finite state machines.
Integr., 1993

On the Specification and Synthesis of Hazard-free Asynchronous Control Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A new state assignment technique for asynchronous finite state machines.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State Machines.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

ESP: An Executable Specification Language for Mixed Timing Control Circuits.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992
Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1987
Synthesis of self-timed VLSI circuits from graph-theoretic specifications.
PhD thesis, 1987

A Method of Abstraction for Petri Nets.
Proceedings of the Second International Workshop on Petri Nets and Performance Models, 1987

1986
On the models for designing VLSI asynchronous digital systems.
Integr., 1986

Design of VLSI Asynchronous FIFO Queues for Packet Communication Networks.
Proceedings of the International Conference on Parallel Processing, 1986


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