Tao Chen

Affiliations:
  • PLA Information Engineering University (Zhengzhou Institute of Information Science and Technology), Department of Microelectronics, Zhengzhou, China


According to our database1, Tao Chen authored at least 11 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A Domain-Specific DMA Structure for Per-channel Processing-based CNN Accelerator.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC.
Frontiers Inf. Technol. Electron. Eng., 2022

A side-channel-attack countermeasure for elliptic curve point multiplication based on dynamic power compensation.
IEICE Electron. Express, 2022

2021
A high-efficient and low-cost secure AMBA framework utilizing configurable data encryption modeling against probe attacks.
IEICE Electron. Express, 2021

An Efficient Module Arithmetic Logic Unit in Dual Field for Internet of Things Applications.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2019
An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processor.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Transparent Buffer Management: An Intra-cluster Task Scheduling Method Based on Dynamic Virtual Channel.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2015
Study and implementation of cluster hierarchical memory system of multicore cryptographic processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2008
The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing.
Proceedings of the International Conference on Embedded Software and Systems, 2008

2007
Design and Implementation of a High-Speed Reconfigurable Modular Arithmetic Unit.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007


  Loading...