Tarek A. El-Moselhy

According to our database1, Tarek A. El-Moselhy authored at least 13 papers between 2008 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2016
A Multiscale Strategy for Bayesian Inference Using Transport Maps.
SIAM/ASA J. Uncertain. Quantification, 2016

2014
Calculation of Generalized Polynomial-Chaos Basis Functions and Gauss Quadrature Rules in Hierarchical Uncertainty Quantification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
Efficient Uncertainty Quantification for the Periodic Steady State of Forced and Autonomous Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012
Bayesian inference with optimal maps.
J. Comput. Phys., 2012

2011
Variation-aware stochastic extraction with large parameter dimensionality: Review and comparison of state of the art intrusive and non-intrusive techniques.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
Field solver technologies for variation-aware interconnect parasitic extraction.
PhD thesis, 2010

Variation-aware interconnect extraction using statistical moment preserving model order reduction.
Proceedings of the Design, Automation and Test in Europe, 2010

Stochastic dominant singular vectors method for variation-aware extraction.
Proceedings of the 47th Design Automation Conference, 2010

2009
A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapes.
Proceedings of the 46th Design Automation Conference, 2009

2008
A capacitance solver for incremental variation-aware extraction.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters.
Proceedings of the 45th Design Automation Conference, 2008


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