Te-Kuang Chiang

According to our database, Te-Kuang Chiang authored at least 5 papers between 2009 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Nanosheet FET: A new subthreshold current model caused by interface-trapped-charge and its application for evaluation of subthreshold logic gate.

Te-Kuang Chiang

Microelectron. J., 2020

2017

A new short-channel-effect-degraded subthreshold behavior model for elliptical gate-all-around MOSFET.

Te-Kuang Chiang, Ying-Wen Ko, Hong-Wun Gao, Yeong-Her Wang

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2013

A novel scaling theory for fully-depleted omega-gate (ΩG) MOSFETs.

Hong-Wun Gao, Te-Kuang Chiang

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2009

A new two-dimensional subthreshold behavior model for the short-channel asymmetrical dual-material double-gate (ADMDG) MOSFET's.

Te-Kuang Chiang

Microelectron. Reliab., 2009

A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET's.

Te-Kuang Chiang

Microelectron. Reliab., 2009