Tetsuo Nakano

According to our database, Tetsuo Nakano authored at least 5 papers between 1989 and 1994.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1994

A 120-MHz BiCMOS superscalar RISC processor.

Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura

IEEE J. Solid State Circuits, April, 1994

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor.

Fumio Murabayashi, Takashi Hotta, Shigeya Tanaka, Tatsumi Yamauchi, Hiromichi Yamada, Tetsuo Nakano, Yutaka Kobayashi, Tadaaki Bandoh

IEEE J. Solid State Circuits, March, 1994

1991

PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor.

Kozaburo Kurita, Takashi Hotta, Tetsuo Nakano, Nobuaki Kitamura

IEEE J. Solid State Circuits, April, 1991

1990

A 70-MHz 32-b microprocessor with 1.0- mu m BiCMOS macrocell library.

Takashi Hotta, Tadaaki Bandoh, Atsuo Hotta, Tetsuo Nakano, Shoji Iwamoto, Shigemi Adachi

IEEE J. Solid State Circuits, June, 1990

1989

A high performance BiCMOS 32-bit microprocessor.

Yasuhiro Nakatsuka, Takashi Hotta, Shigeya Tanaka, Tadaaki Bandoh, Ryuichi Satomura, Syuichi Nakagami, Tetsuo Nakano, Atsuo Hotta, Takashi Moriyama, Shigemi Adachi, Shoji Iwamoto

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989