Ting Wei Chiang

According to our database1, Ting Wei Chiang authored at least 2 papers in 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2007
An efficient gate delay model for VLSI design.
Proceedings of the 25th International Conference on Computer Design, 2007

A technique for selecting CMOS transistor orders.
Proceedings of the 25th International Conference on Computer Design, 2007


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