Tomasz Madajczak

According to our database, Tomasz Madajczak authored at least 5 papers between 2004 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2006

Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs.

Tomasz Madajczak, Henryk Krawczyk

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

2005

Taking Advantage of the SHECS-Based Critical Sections in the Shared Memory Parallel Architectures.

Tomasz Madajczak

Proceedings of the Parallel Processing and Applied Mathematics, 2005

Implementing Critical Sections with the Shared Explicit Cache System in the Shared Memory Parallel Architectures.

Tomasz Madajczak, Henryk Krawczyk

Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

2004

An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures.

Tomasz Madajczak

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Optimal Programming of Critical Sections in Modern Network Processors under Performance Requirements.

Henryk Krawczyk, Tomasz Madajczak

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004