Trung A. Diep

According to our database1, Trung A. Diep authored at least 8 papers between 1993 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2004
A case for shared instruction cache on chip multiprocessors running OLTP.
SIGARCH Computer Architecture News, 2004

2003
Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

2002
Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

1995
VMW: A Visualization-Based Microarchitecture Workbench.
IEEE Computer, 1995

Performance Evaluation of the PowerPC 620 Microarchitecture.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures.
Proceedings of the Digest of Papers: FTCS-25, 1995

1993
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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