Uisub Shin
Orcid: 0000-0002-3326-8332
According to our database1,
Uisub Shin
authored at least 10 papers
between 2018 and 2024.
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Bibliography
2024
33.3 MiBMI: A 192/512-Channel 2.46mm² Miniaturized Brain-Machine Interface Chipset Enabling 31-Class Brain-to-Text Conversion Through Distinctive Neural Codes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
NeuralTree: A 256-Channel 0.227-μJ/Class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC.
IEEE J. Solid State Circuits, 2022
A 16-Channel Low-Power Neural Connectivity Extraction and Phase-Locked Deep Brain Stimulation SoC.
CoRR, 2022
NeuralTree: A 256-Channel 0.227μJ/class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC.
CoRR, 2022
A 256-Channel 0.227µJ/class Versatile Brain Activity Classification and Closed-Loop Neuromodulation SoC with 0.004mm<sup>2</sup>-1.51 µW/channel Fast-Settling Highly Multiplexed Mixed-Signal Front-End.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
Closed-Loop Neural Prostheses With On-Chip Intelligence: A Review and a Low-Latency Machine Learning Model for Brain State Detection.
IEEE Trans. Biomed. Circuits Syst., 2021
2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2018
Mismatch-tolerant read-in IC with voltage-drop compensation for infrared scene projectors [IEICE Electronics Express Vol. 15(2018) No. 11 pp. 20180182].
IEICE Electron. Express, 2018
Mismatch-tolerant read-in IC with voltage-drop compensation for infrared scene projectors.
IEICE Electron. Express, 2018