Ulrich Brenner

Affiliations:
  • University of Bonn, Germany


According to our database1, Ulrich Brenner authored at least 19 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2023
BonnLogic: Delay optimization by And-Or Path restructuring.
Integr., March, 2023

2022
Constructing depth-optimum circuits for adders and And-Or paths.
Discret. Appl. Math., 2022

Delay Optimization of Combinational Logic by AND-OR Path Restructuring.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2019
Faster Carry Bit Computation for Adder Circuits with Prescribed Arrival Times.
ACM Trans. Algorithms, 2019

2018
<i>γ</i>-Soft packings of rectangles.
Comput. Geom., 2018

2017
Faster Adder Circuits for Inputs with Prescribed Arrival Times.
CoRR, 2017

2015
BonnPlace: A Self-Stabilizing Placement Framework.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2013
BonnPlace Legalization: Minimizing Movement by Iterative Augmentation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012
VLSI legalization with minimum perturbation by iterative augmentation.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2008
Analytical Methods in Placement.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A faster polynomial algorithm for the unbalanced Hitchcock transportation problem.
Oper. Res. Lett., 2008

2006
Theory and Practice of VLSI Placement
PhD thesis, 2006

2005
Faster and better global placement by a new transportation algorithm.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Legalizing a placement with minimum total movement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Almost optimum placement legalization by minimum cost flow and dynamic programming.
Proceedings of the 2004 International Symposium on Physical Design, 2004

2003
An effective congestion-driven placement framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2001
Worst-case ratios of networks in the rectilinear plane.
Networks, 2001

2000
Faster Optimal Single-Row Placement with Fixed Ordering.
Proceedings of the 2000 Design, 2000


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