Upasna Vishnoi

According to our database, Upasna Vishnoi authored at least 5 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Highly area- and energy-efficient QR-decomposition CMOS macros for a wide range of applications.

Upasna Vishnoi

PhD thesis, 2017

2016

A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency.

Upasna Vishnoi, Michael Meixner, Tobias G. Noll

J. Signal Process. Syst., 2016

2013

A family of modular area- and energy-efficient QRD-accelerator architectures.

Upasna Vishnoi, Tobias G. Noll

Proceedings of the 2013 International Symposium on System on Chip, 2013

Cross-layer optimization of QRD accelerators.

Upasna Vishnoi, Tobias G. Noll

Proceedings of the ESSCIRC 2013, 2013

2012

An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks.

Upasna Vishnoi, Michael Meixner, Tobias G. Noll

Proceedings of the IEEE 25th International SOC Conference, 2012