Tobias G. Noll
According to our database1,
Tobias G. Noll
authored at least 101 papers
between 1984 and 2018.
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Bibliography
2018
Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency.
J. Signal Process. Syst., 2017
Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems.
ACM Comput. Surv., 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
2016
A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency.
J. Signal Process. Syst., 2016
A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
2015
Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations.
ACM Comput. Surv., 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
On the use of analytical techniques for reliability analysis in presence of hardware-induced errors.
Proceedings of the 13th IEEE International Conference on Industrial Informatics, 2015
2014
Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
Optimal data path widths for energy- and area-efficient Max-Log-MAP based LTE Turbo decoders.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Based on Accurate Cost Models.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks.
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 20th European Symposium on Artificial Neural Networks, 2012
2011
Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2010
Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers.
J. Signal Process. Syst., 2010
MATLAB Meets LEGO Mindstorms - A Freshman Introduction Course Into Practical Engineering.
IEEE Trans. Educ., 2010
A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010
2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
J. Signal Process. Syst., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis.
J. Syst. Archit., 2008
Proceedings of the Embedded Computer Systems: Architectures, 2008
Design of a Pareto-optimization environment and its application to motion estimation.
Proceedings of the International Workshop on Multimedia Signal Processing, 2008
Proceedings of the Medical Imaging 2008: Image Processing, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures.
J. Syst. Archit., 2007
Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures.
J. Syst. Archit., 2007
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
Programmable Architectures for Realtime Music Decompression.
Proceedings of the Parallel Computing: Architectures, 2007
Proceedings of the FPL 2007, 2007
Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain.
J. VLSI Signal Process., 2006
Proceedings of the Embedded Computer Systems: Architectures, 2006
Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Application specific instruction processor based implementation of a GNSS receiver on an FPGA.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
J. VLSI Signal Process., 2005
Proceedings of the Embedded Computer Systems: Architectures, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
IEEE J. Solid State Circuits, 2004
Proceedings of the Visual Communications and Image Processing 2004, 2004
Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets.
Proceedings of the Computer Systems: Architectures, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2002
Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.
J. VLSI Signal Process., 2002
Object based refinement of motion vector fields applying probabilistic homogenization rules.
IEEE Trans. Consumer Electron., 2002
Implementation of scalable power and area efficient high-throughput Viterbi decoders.
IEEE J. Solid State Circuits, 2002
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002
2000
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000
1998
Device visualization for interventional MRI using local magnetic fields: Basic theory and its application to catheter visualization.
IEEE Trans. Medical Imaging, 1998
IEEE J. Solid State Circuits, 1998
A hybrid equalizer merging the advantages of Baud spaced and fractionally spaced equalizers.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
Proceedings of the Bildverarbeitung für die Medizin: Algorithmen, 1998
Verbesserung der Dynamik und Ortsauflösung in der Ultraschalldiagnostik durch die Kombination kodierter Anregung und tiefenangepaßter Mismatched-Filterung.
Proceedings of the Bildverarbeitung für die Medizin: Algorithmen, 1998
1997
A novel systematic mapping approach for highly efficient multiplexed FIR-filter architectures.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
1996
Artefaktreduzierung in der ultraschnellen Magnetresonanz-Bildgebung mittels inverser Filterung im Ortsfrequenzbereich.
Proceedings of the Bildverarbeitung für die Medizin: Algorithmen, 1996
Korrektur der Phasenaberration in Ultraschallaufnahmen durch das Dynamic-Time-Warping Verfahren.
Proceedings of the Bildverarbeitung für die Medizin: Algorithmen, 1996
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996
1995
Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications.
IEEE J. Solid State Circuits, March, 1995
1994
A 60-MBaud Single-Chip QAM-Processor for the Complete Base-Band Signal Processing of QAM Demodulators.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1991
J. VLSI Signal Process., 1991
1990
Proceedings of the 1990 International Conference on Acoustics, 1990
1989
Proceedings of the IEEE International Conference on Acoustics, 1989
1984
Proceedings of the IEEE International Conference on Acoustics, 1984
Proceedings of the IEEE International Conference on Acoustics, 1984