Usha Sandeep Mehta
Orcid: 0000-0002-9917-5518
According to our database1,
Usha Sandeep Mehta
authored at least 13 papers
between 2009 and 2018.
Collaborative distances:
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Bibliography
2018
2016
2015
Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
A Hamming code based technique to resolve the bit flip impact on compressed VLSI test data in IP core based SoC.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
2011
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method.
VLSI Design, 2011
VLSI Design, 2011
Proceedings of the ICWET '11 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 25, 2011
2010
Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds? - A Survey.
VLSI Design, 2010
Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead.
J. Electron. Test., 2010
Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009