Vaibhav Neema

Orcid: 0000-0003-0922-373X

According to our database1, Vaibhav Neema authored at least 11 papers between 2010 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A Hardware Attack Secure SRAM: A HAS-16T SRAM Cell Resistant to Side Channel Attacks and Fault-Injection Attacks.
IEEE Trans. Very Large Scale Integr. Syst., April, 2026

DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration.
CoRR, April, 2026

2025
Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack.
ACM Trans. Design Autom. Electr. Syst., May, 2025

Secure SRAM Memory Design for Secret Data Protection Against Data Imprinting and Power Attack.
J. Circuits Syst. Comput., March, 2025

Radiation-Tolerant SRAM for Satellite Image Compression Systems: A Hybrid Memory Array Approach.
Int. J. Circuit Theory Appl., 2025

2024
Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique.
Microelectron. J., 2024

2021
A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications.
J. Circuits Syst. Comput., 2021

2019
An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network.
Microelectron. J., 2019

Intelligent Traffic Light Controller: A Solution for Smart City Traffic Problem.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2015
A novel leakage reduction DOIND approach for nanoscale domino logic circuits.
Proceedings of the Eighth International Conference on Contemporary Computing, 2015

2010
Novel circuit technique for reduction of active drain current in low leakage digital VLSI circuits.
Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010


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