Santosh Kumar Vishvakarma
Orcid: 0000-0003-4223-0077
According to our database1,
Santosh Kumar Vishvakarma
authored at least 71 papers
between 2011 and 2024.
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Bibliography
2024
Circuits Syst. Signal Process., January, 2024
QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit.
IEEE Access, 2024
2023
Circuits Syst. Signal Process., December, 2023
Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators.
Circuits Syst. Signal Process., October, 2023
Clock Gating-Based Effectual Realization of Stochastic Hyperbolic Tangent Function for Deep Neural Hardware Accelerators.
Circuits Syst. Signal Process., October, 2023
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks.
ACM Trans. Reconfigurable Technol. Syst., September, 2023
A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency.
J. Circuits Syst. Comput., March, 2023
A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse Extension Logic.
J. Circuits Syst. Comput., March, 2023
Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
IEEE Access, 2023
Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators.
Proceedings of the Internet of Things. Advances in Information and Communication Technology, 2023
2022
Int. J. Imaging Syst. Technol., 2022
Early breast cancer diagnosis using cogent activation function-based deep learning implementation on screened mammograms.
Int. J. Imaging Syst. Technol., 2022
Data multiplexed and hardware reused architecture for deep neural network accelerator.
Neurocomputing, 2022
Circuits Syst. Signal Process., 2022
BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator.
Circuits Syst. Signal Process., 2022
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2021
IEEE Open J. Circuits Syst., 2021
IEEE Open J. Circuits Syst., 2021
VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators.
Microprocess. Microsystems, 2021
IEEE Access, 2021
Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the 13th International Conference on COMmunication Systems & NETworkS, 2021
2020
A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application.
J. Circuits Syst. Comput., 2020
Int. J. Commun. Syst., 2020
J. Electron. Test., 2020
A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture.
Circuits Syst. Signal Process., 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
2019
Proceedings of the Guide to Ambient Intelligence in the IoT Environment, 2019
An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network.
Microelectron. J., 2019
Microelectron. J., 2019
SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit.
IET Comput. Digit. Tech., 2019
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM.
Circuits Syst. Signal Process., 2019
Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
2018
An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells.
Microelectron. Reliab., 2018
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design.
Integr., 2018
Int. J. Circuit Theory Appl., 2018
Robust task-space motion control of a mobile manipulator using a nonlinear control with an uncertainty estimator.
Comput. Electr. Eng., 2018
IEEE Access, 2018
A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Design and investigation of variability aware sense amplifier for low power, high speed SRAM.
Microelectron. J., 2017
J. Low Power Electron., 2017
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations.
Microelectron. J., 2016
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance.
Circuits Syst. Signal Process., 2016
Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications.
Circuits Syst. Signal Process., 2016
Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
2015
Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET.
Microelectron. J., 2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small I<sub>cell</sub> SRAM Using FinFET.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
2013
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
2012
Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions.
Microelectron. J., 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
2011
Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlN<sub>x</sub>) symmetric double gate MOSFET.
Microelectron. J., 2011