Valerie Lines

According to our database1, Valerie Lines authored at least 2 papers between 2000 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2000
66MHz 2.3M Ternary Dynamic Content Addressable Memory.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000


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