Vijay Savani

Orcid: 0000-0002-0874-5360

According to our database¹, Vijay Savani authored at least 4 papers between 2015 and 2026.

Collaborative distances:

Timeline

Book In proceedings Article PhD thesis Dataset Other

2026

A hybrid 16-bit Ripple Carry Adder with Doublet Transmission Gate-based Compressor for performance boost.

[DOI]

Integr., 2026

2024

Design and Analysis of Low-Voltage and Low-Power 19T FinFET-TGDI-Based Hybrid Full Adders.

[DOI]

J. Circuits Syst. Comput., January, 2024

2018

Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator.

[DOI]

Microelectron. J., 2018

2015

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology.

[DOI]

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015