Vijaya Bhadauria

Orcid: 0000-0002-3547-9475

According to our database1, Vijaya Bhadauria authored at least 10 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
An ultra-wide band IIP3 of 38.2 dBm and conversion gain of 17.95 dB down conversion Gilbert mixer for 5G internet of things applications.
Wirel. Networks, May, 2023

2022
High-throughput, area-efficient hardware architecture of CABAC-Binarization for UHD applications.
Microelectron. J., 2022

A 12-bit SC3 partially segmented current steering DAC with improved SFDR and bandwidth.
Int. J. Circuit Theory Appl., 2022

2021
An ultra-low-power bulk-driven subthreshold super class-AB rail-to-rail CMOS OTA with enhanced small and large signal performance suitable for large capacitive loads.
Microelectron. J., 2021

A Low-Voltage Two-Stage Enhanced Gain Bulk-Driven Floating Gate OTA.
J. Circuits Syst. Comput., 2021

Linearity Improvement of Bulk Driven Floating Gate OTA Using Cross-Bulk and Quasi-Bulk Techniques.
J. Circuits Syst. Comput., 2021

2017
Fully Differential Operational Transconductance Amplifier with Enhanced Phase Margin and Gain for Ultra-Low-Power Circuits.
J. Low Power Electron., 2017

Fully Differential, Bulk-Driven, Class AB, Sub-Threshold OTA With Enhanced Slew Rates and Gain.
J. Circuits Syst. Comput., 2017

2016
Sub-threshold, cascode compensated, bulk-driven OTAs with enhanced gain and phase-margin.
Microelectron. J., 2016

2010
A tunable transconductor with high linearity.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010


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