Vijeta Rathore

Orcid: 0000-0001-5439-1885

According to our database1, Vijeta Rathore authored at least 9 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors.
IEEE Trans. Computers, 2021

2020
Scalable techniques for extending lifetime reliability of manycore systems
PhD thesis, 2020

2019
Towards Scalable Lifetime Reliability Management for Dark Silicon Manycore Systems.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

LifeGuard: A Reinforcement Learning-Based Task Mapping Strategy for Performance-Centric Aging Management.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

LifeSim: A lifetime reliability simulator for manycore systems.
Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018

2016
Performance Constraint-Aware Task Mapping to Optimize Lifetime Reliability of Manycore Systems.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

2011
Providing Network Performance Isolation in VDE-Based Cloud Computing Systems.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011


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