Siew-Kei Lam

Proceedings of the International Conference on Field Programmable Technology, 2017

Group Cost-sensitive Boosting with Multi-scale Decorrelated Filters for Pedestrian Detection.

[BibT_eX]

[DOI]

Chengju Zhou

Siew-Kei Lam

Proceedings of the British Machine Vision Conference 2017, 2017

2016

Enhanced low-complexity pruning for corner detection.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2016

Algorithms for bi-objective multiple-choice hardware/software partitioning.

[BibT_eX]

[DOI]

Wenjun Shi

Comput. Electr. Eng., 2016

Real-time road traffic density estimation using block variance.

[BibT_eX]

[DOI]

Kratika Garg

Vedika Agarwal

Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision, 2016

Shortest Partial Path First Algorithm for Reconfigurable Processor Array with Faults.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016

Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors.

[BibT_eX]

[DOI]

Deshya Wijesundera

Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Bounded iterative thresholding for lumen region detection in endoscopic images.

[BibT_eX]

[DOI]

Pon Nidhya Elango

Proceedings of the 14th International Conference on Control, 2016

Reducing Access Latency in Virtual Machine Assignments.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

2015

Algorithmic aspects of graph reduction for hardware/software partitioning.

[BibT_eX]

[DOI]

Guiyuan Jiang

Jizhou Sun

J. Supercomput., 2015

Nonparametric Technique Based High-Speed Road Surface Detection.

[BibT_eX]

[DOI]

IEEE Trans. Intell. Transp. Syst., 2015

KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs.

[BibT_eX]

[DOI]

Kratika Garg

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Adaptive Window Strategy for High-Speed and Robust KLT Feature Tracker.

[BibT_eX]

[DOI]

Gauri Ravindra Tulsulkar

Proceedings of the Image and Video Technology - 7th Pacific-Rim Symposium, 2015

Rapid estimation of DSPs utilization for efficient high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Fast Replica Placement and Update Strategies in Tree Networks.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015

2014

Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2014

Parallel reconfiguration algorithms for mesh-connected processor arrays.

[BibT_eX]

[DOI]

J. Supercomput., 2014

Rapid evaluation of custom instruction selection approaches with FPGA estimation.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Addressing Productivity Challenges in Domain-Specific Reconfigurable Platforms: A Case Study on Extended Kalman Filter-Based Motor Control.

[BibT_eX]

[DOI]

J. Low Power Electron., 2014

Algorithmic Aspects for Bi-Objective Multiple-Choice Hardware/Software Partitioning.

[BibT_eX]

[DOI]

Wenjun Shi

Proceedings of the Sixth International Symposium on Parallel Architectures, 2014

Stereo based ROIs generation for detecting pedestrians in close proximity.

[BibT_eX]

[DOI]

Proceedings of the 17th International IEEE Conference on Intelligent Transportation Systems, 2014

Vision-based pedestrian tracking system using color and motion cue.

[BibT_eX]

[DOI]

Tushar Shah

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Mask-based non-maximal suppression with iterative pruning for low-complexity corner detection.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Automated thresholding for low-complexity corner detection.

[BibT_eX]

[DOI]

Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013

Efficient heuristic and tabu search for hardware/software partitioning.

[BibT_eX]

[DOI]

Pu Wang

J. Supercomput., 2013

FPGA-aware techniques for rapid generation of profitable custom instructions.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Iris Recognition Using Stable Dark Features.

[BibT_eX]

[DOI]

J. Comput., 2013

Real-Time Image Resizing Hardware Accelerator for Object Detection Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Hardware-Software Codesign of EKF-Based Motor Control for Domain-Specific Reconfigurable Platform.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays.

[BibT_eX]

[DOI]

Yuanbo Zhu

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Modelling communication overhead for accessing local memories in hardware accelerators.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

Iris Recognition of Defocused Images for Mobile phones.

[BibT_eX]

[DOI]

Int. J. Pattern Recognit. Artif. Intell., 2012

Low-complexity pruning for accelerating corner detection.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Exploiting stable features for iris recognition of defocused images.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Reconfiguration Algorithms for Degradable VLSI Arrays with Switch Faults.

[BibT_eX]

[DOI]

Yuanbo Zhu

Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

Area-time estimation of C-based functions for design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011

Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Instruction set customization for area-constrained FPGA designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Compiler-assisted technique for rapid performance estimation of FPGA-based processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Utilizing Dark Features for Iris Recognition in Less Constrained Environments.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

Automatic Compilation of C Applications for FPGA-Based Hardware Acceleration.

[BibT_eX]

[DOI]

Lieu My Chuong

Chai-Soon Lim

Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis.

[BibT_eX]

[DOI]

Sharad Sinha

Udit Dhawan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

Selecting profitable custom instructions for reconfigurable processors.

[BibT_eX]

[DOI]

Tao Li

Xicheng Lu

J. Syst. Archit., 2010

An efficient edge and corner detector.

[BibT_eX]

[DOI]

Song Yang

Proceedings of the 11th International Conference on Control, 2010

Performance estimation framework for FPGA-based processors.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

Accelerating shortest path computations in hardware.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Automation Science and Engineering, 2010

Architecture-Aware Custom Instruction Generation for Reconfigurable Processors.

[BibT_eX]

[DOI]

Amit Kumar Singh

Proceedings of the Reconfigurable Computing: Architectures, 2010

Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2009

Rapid design of area-efficient custom instructions for reconfigurable embedded processing.

[BibT_eX]

[DOI]

J. Syst. Archit., 2009

Run-time management of custom instructions on a partially reconfigurable architecture.

[BibT_eX]

[DOI]

Huang Fan

Int. J. Inf. Commun. Technol., 2009

Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA.

[BibT_eX]

[DOI]

Lieu My Chuong

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Rapid design exploration framework for application-aware customization of soft core processors.

[BibT_eX]

[DOI]

Amit Kumar Singh

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection.

[BibT_eX]

[DOI]

Tao Li

Xicheng Lu

Proceedings of the 8th IEEE/ACIS International Conference on Computer and Information Science, 2009

2008

A Short Course on Implementing FPGA Based Digital Systems.

[BibT_eX]

[DOI]

George Rosario Jagadeesh

Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

2007

Rapid Area-Time Estimation Technique for Porting C-based Applications onto FPGA platforms.

[BibT_eX]

[DOI]

Lieu My Chuong

Scalable Comput. Pract. Exp., 2007

Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

Rapid generation of custom instructions using predefined dataflow structures.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

Efficient Architectures for Segmentation of Endoscopic Images in Micro-Robotic Auto Navigation Systems.

[BibT_eX]

[DOI]

C. S. Lim

Int. J. Humanoid Robotics, 2006

Efficient management of custom instructions for run-time reconfigurable instruction set processors.

[BibT_eX]

[DOI]

Bharathi N. Krishnan

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Energy Efficient Cache Tuning with Performance Bound.

[BibT_eX]

[DOI]

Leipo Yan

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors.

[BibT_eX]

[DOI]

Mohammed Shoaib

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005

VLSI-efficient schemes for high-speed construction of tangent graph.

[BibT_eX]

[DOI]

K. Sridharan

Robotics Auton. Syst., 2005

Morphable Structures for Reconfigurable Instruction Set Processors.

[BibT_eX]

[DOI]

Yun Deng

Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004

Hardware-efficient schemes for logarithmic approximation and binary search with application to visibility graph construction.

[BibT_eX]

[DOI]

K. Sridharan

IEEE Trans. Ind. Electron., 2004

Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System.

[BibT_eX]

[DOI]

Mishra Suman

IEEE Trans. Computers, 2004

High-throughput image rotation using sign-prediction based redundant cordic algorithm.

[BibT_eX]

Suchitra Sathyanarayana

Proceedings of the 2004 International Conference on Image Processing, 2004

2003

Implementing Otsu's thresholding process using area-time efficient logarithmic approximation unit.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Architectural design and analysis toolbox to implement shortest path algorithms in hardware.

[BibT_eX]

[DOI]

K. H. Quek

N. K. Agrawal

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low cost logarithmic techniques for high-precision computations.

[BibT_eX]

[DOI]

Devendra K. Chaudhaiy

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

A linear approximation based hybrid approach for binary logarithmic conversion.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2002

Environment Modelling for Robot Navigation Using VLSI-Efficient Logarithmic Approximation Method.

[BibT_eX]

[DOI]

J. Intell. Robotic Syst., 2002

Study on the Effect of Object to Camera Distance on Polynomial Expansion Coefficients in Barrel Distortion Correction.

[BibT_eX]

[DOI]

Vijayan K. Asari

Proceedings of the 5th IEEE Southwest Symposium on Image Analysis and Interpretation, 2002

An efficient architecture for adaptive progressive thresholding.

[BibT_eX]

[DOI]

Chip-Hong Chang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Fuzzy-ART based image compression for hardware implementation.

[BibT_eX]

[DOI]

C. S. Lim

Vijayan K. Asari

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Incorporating area-time flexibility to a binary signed-digit adder.

[BibT_eX]

[DOI]

Nitin Goyal

Neeraj Tyagi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

High-Speed Environment Representation Scheme for Dynamic Path Planning.

[BibT_eX]

[DOI]

J. Intell. Robotic Syst., 2001

2000

VLSI based hardware accelerator for compute intensive routing applications

[BibT_eX]

[DOI]

Siew-Kei Lam

PhD thesis, 2000

Dynamic multicast routing in VLSI.

[BibT_eX]

[DOI]