Vikas Chauhan

Orcid: 0000-0003-2089-0963

According to our database1, Vikas Chauhan authored at least 15 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Tackling over-smoothing in multi-label image classification using graphical convolution neural network.
Evol. Syst., October, 2023

Video Anomaly Latent Training GAN (VALT GAN): Enhancing Anomaly Detection Through Latent Space Mining.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2023

Unveiling the Dynamics of Free Trade: A Big Data Analytics Perspective on Domestic, Economic, and Strategic Dimensions.
Proceedings of the 6th International Conference on Contemporary Computing and Informatics, 2023

Analysis and Configuration of IoT Sensors in Smart Structure by Employing QR Code Generator.
Proceedings of the 6th International Conference on Contemporary Computing and Informatics, 2023

2022
Pairnorm based Graphical Convolution Network for zero-shot multi-label classification.
Eng. Appl. Artif. Intell., 2022

Region of Interest focused MRI to Synthetic CT Translation using Regression and Classification Multi-task Network.
CoRR, 2022

Randomized neural networks for multilabel classification.
Appl. Soft Comput., 2022

Multi-label classifier for protein sequence using heuristic-based deep convolution neural network.
Appl. Intell., 2022

An Approach for Implementing Comprehensive Reconnaissance for Bug Bounty Hunters.
Proceedings of the 5th International Conference on Contemporary Computing and Informatics, 2022

2020
Multi-Label classifier based on Kernel Random Vector Functional Link Network.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

2018
On the Construction of Hierarchical Broad Learning Neural Network: An Alternative Way of Deep Learning.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2018

2016
Code-modulated embedded test for phased arrays.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2006
Bandwidth Efficient String Reconciliation Using Puzzles.
IEEE Trans. Parallel Distributed Syst., 2006

2004
Reconciliation puzzles [separately hosted strings reconciliation].
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004


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