Vikas Nehra

According to our database, Vikas Nehra authored at least 2 papers between 2019 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications.

Ashish Sura, Vikas Nehra

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2019

Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms.

Piyush Tankwal, Vikas Nehra, Brajesh Kumar Kaushik

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019