Vikas Nehra

Orcid: 0000-0001-7016-1350

According to our database¹, Vikas Nehra authored at least 2 papers between 2019 and 2021.

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2021

Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications.

[DOI]

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2019

Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms.

[DOI]

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019