Brajesh Kumar Kaushik
Orcid: 0000-0002-6414-0032Affiliations:
- Indian Institute of Technology Roorkee, Roorkee, India
According to our database1,
Brajesh Kumar Kaushik
authored at least 76 papers
between 2007 and 2023.
Collaborative distances:
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on orcid.org
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on d-nb.info
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on iitr.ac.in
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Bibliography
2023
Novel Radiation Hardened DSOT-MRAM Read Peripheral Circuit With Reduced Sensitive Nodes.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
Microelectron. J., November, 2023
Quantum Inf. Process., April, 2023
Circuits Syst. Signal Process., February, 2023
2022
IEEE Trans. Instrum. Meas., 2022
A Bilevel Multi-Fidelity Polynomial Chaos Approach for the Uncertainty Quantification of MWCNT Interconnect Networks With Variable Imperfect Contact Resistances.
IEEE Access, 2022
2021
Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure.
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Intell. Transp. Syst., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Efficient Hardware Implementation of DNN-Based Speech Enhancement Algorithm With Precise Sigmoid Activation Function.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Quantum Inf. Process., 2021
Microelectron. J., 2021
Vertical traversal approach towards TSVs optimisation over multilayer network on chip (NoC).
Microelectron. J., 2021
J. Syst. Archit., 2021
2020
IEEE Trans. Circuits Syst., 2020
Development of Dopamine Sensor Using Silver Nanoparticles and PEG-Functionalized Tapered Optical Fiber Structure.
IEEE Trans. Biomed. Eng., 2020
Fast and robust video stabilisation with preserved intentional camera motion and smear removal for infrared video.
IET Image Process., 2020
IET Circuits Devices Syst., 2020
IEEE Access, 2020
Statistical Analysis of Temperature Variability on the Write Efficiency of Spin-Orbit Torque MRAM using Polynomial Chaos Metamodels.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Analytical modelling and device design optimisation of epitaxial layer-based III-V tunnel FET.
IET Circuits Devices Syst., 2019
Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Low Restoration-Energy Differential Spin Hall Effect MRAM for High-Speed Nonvolatile SRAM Application.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
2018
Transmission Coefficient Matrix Modeling of Spin-Torque-Based $n$ -Qubit Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Temperature-dependent modeling and performance analysis of coupled MLGNR interconnects.
Int. J. Circuit Theory Appl., 2018
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018
2017
Variation-aware widely tunable nanoscale design of CMOS active inductor-based RF bandpass filter.
Int. J. Circuit Theory Appl., 2017
Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Reconfigurable Architecture-Based Implementation of Non-uniformity Correction for Long Wave IR Sensors.
Proceedings of International Conference on Computer Vision and Image Processing, 2016
2015
Crosstalk noise modeling of multiwall carbon nanotube (MWCNT) interconnects using finite-difference time-domain (FDTD) technique.
Microelectron. Reliab., 2015
Microelectron. J., 2015
Crosstalk Induced Delay Analysis of Randomly Distributed Mixed CNT Bundle Interconnect.
J. Circuits Syst. Comput., 2015
Proceedings of Fifth International Conference on Soft Computing for Problem Solving, 2015
A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Accurate Numerical Model for Crosstalk Analysis of SWCNT Bundle Interconnects Using FDTD Method.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
2014
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Design and analysis of noise margin, write ability and read stability of organic and hybrid 6-T SRAM cell.
Microelectron. Reliab., 2014
An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method.
Microelectron. J., 2014
Analysis of electrical parameters of organic thin film transistors based on thickness variation in semiconducting and dielectric layers.
IET Circuits Devices Syst., 2014
High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
2013
Analytical modeling and parameter extraction of top and bottom contact structures of organic thin film transistors.
Microelectron. J., 2013
Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects.
Microelectron. J., 2013
J. Low Power Electron., 2013
Analysis of electrode thickness variation on performance parameters of polymer thin film transistors using device simulation.
Int. J. Adv. Intell. Paradigms, 2013
Analysis of static and dynamic performance of organic inverter circuits based on dual and single gate organic thin film transistors.
IET Circuits Devices Syst., 2013
A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-T<sub>ox </sub>in CMOS VLSI Circuits.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-<i>k</i> Spacers.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
2012
Channel length variation effect on performance parameters of organic field effect transistors.
Microelectron. J., 2012
Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Propagation Delay Analysis for Bundled Multi-Walled CNT in Global VLSI Interconnects.
Proceedings of the Second International Conference on Soft Computing for Problem Solving, 2012
Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012
Comparison of crosstalk delay between single and bundled SWNT for global VLSI interconnects.
Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012
Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Analysis of Contact Resistance Effect on Performance of Organic Thin Film Transistors.
Proceedings of the International Symposium on Electronic System Design, 2012
2011
Repeater insertion in crosstalk-aware inductively and capacitively coupled interconnects.
Int. J. Circuit Theory Appl., 2011
Top and Bottom Gate Polymeric Thin Film Transistor Analysis through Two Dimensional Numerical Device Simulation.
Proceedings of the International Conference on Soft Computing for Problem Solving (SocProS 2011) December 20-22, 2011, 2011
2010
Microelectron. J., 2010
Effect of Distributed Shield Insertion on Crosstalk in Inductively Coupled VLSI Interconnects
CoRR, 2010
Proceedings of the Information and Communication Technologies - International Conference, 2010
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010
Effect of Mutual Inductance and Coupling Capacitance on Propagation Delay and Peak Overshoot in Dynamically Switching Inputs.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010
Implementation of Coordinate Rotation Algorithm for Digital Phase Locked Loop System in In-Phase and Quadrature Channel Signal Processing.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects.
Microelectron. J., 2008
2007
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load.
Integr., 2007
Crosstalk Analysis of an Inductively and Capacitively Coupled Interconnect Driven by a CMOS Gate.
Proceedings of the 10th International Conference on Information Technology, 2007