Viktor Razilov

According to our database, Viktor Razilov authored at least 9 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Conflict Management in Vector Register Files.

Viktor Razilov, Ipek Geçin, Emil Matús, Gerhard P. Fettweis

ACM Trans. Archit. Code Optim., March, 2025

On Memory Systems in Parallel Architectures.

Viktor Razilov

PhD thesis, 2025

Routing in Multi-Chip Platforms with Hybrid Interconnects.

Joy Halder, Nayeem Ahmed, Viktor Razilov, Emil Matús, Gerhard P. Fettweis

Proceedings of the 18th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2025

2024

Access Interval Prediction by Partial Matching for Tightly Coupled Memory Systems.

Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis

Int. J. Parallel Program., April, 2024

Implementation of the Tagged Geometric History Length Access Interval Predictor.

Viktor Razilov, Emil Matús, Gerhard P. Fettweis

Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

2023

Access Interval Prediction with Neural Networks for Tightly Coupled Memory Systems.

Simon Friedrich, Chia-Ying Lin, Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Dual Vector Load for Improved Pipelining in Vector Processors.

Viktor Razilov, Juncen Zhong, Emil Matús, Gerhard P. Fettweis

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023

2022

Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory Systems.

Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

Communications Signal Processing Using RISC-V Vector Extension.

Viktor Razilov, Emil Matús, Gerhard P. Fettweis

Proceedings of the 2022 International Wireless Communications and Mobile Computing, 2022