Robert Wittig

According to our database, Robert Wittig authored at least 23 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Access Interval Prediction by Partial Matching for Tightly Coupled Memory Systems.

Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis

Int. J. Parallel Program., April, 2024

2023

On-Chip Memory Access Reduction for Energy-Efficient Dilated Convolution Processing.

Simon Friedrich, Thomas Nalapat, Robert Wittig, Emil Matús, Gerhard P. Fettweis

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands.

Simon Friedrich, Shambhavi Balamuthu Sampath, Robert Wittig, Manoj Rohit Vemparala, Nael Fasfous, Emil Matús, Walter Stechele, Gerhard P. Fettweis

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Access Interval Prediction with Neural Networks for Tightly Coupled Memory Systems.

Simon Friedrich, Chia-Ying Lin, Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective.

Fabian Kempf, Julian Höfer, Tanja Harbaum, Jürgen Becker, Nael Fasfous, Alexander Frickenstein, Hans-Jörg Vögel, Simon Friedrich, Robert Wittig, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Holger Blume, Jens Benndorf, Darius Grantz, Martin Zeller, Dietmar Engelke, Karl-Heinz Eickel

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Accurate Estimation of Service Rates in Interleaved Scratchpad Memory Systems.

Robert Wittig, Philipp Schulz, Emil Matús, Gerhard P. Fettweis

ACM Trans. Embed. Comput. Syst., 2022

Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory Systems.

Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI.

Mattis Hasler, Sebastian Haas, Robert Wittig, Stefan Scholze, Andreas Dixius, Sebastian Höppner, Gerhard P. Fettweis, Christian Mayr

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021

Architectures and Theoretical Models for Shared Scratchpad Memory Systems.

Robert Wittig

PhD thesis, 2021

Opportunities For A Hardware-Based OPC UA Server Implementation In Industry 4.0.

Zohra Charania, Chris Paul Iatrou, Valentin Khaydarov, Richard Jacob, Robert Wittig, Heiner Bauer, Sebastian Höppner, René Bachmann, Philipp Bauer, Hendrik Deckert, Christian Mayr, Gerhard P. Fettweis, Leon Urbas

Proceedings of the IECON 2021, 2021

2020

Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion.

Mattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Modem Design in the Era of 5G and Beyond: The Need for a Formal Approach.

Robert Wittig, Andrés Goens, Christian Menard, Emil Matús, Gerhard P. Fettweis, Jerónimo Castrillón

Proceedings of the 27th International Conference on Telecommunications, 2020

Balancing Dynamic Scheduling Overhead to Maximize SDF Performance.

Mattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis

Proceedings of the 2nd 6G Wireless Summit, 2020

2019

Probabilistic Models for Off-Line Arbiters in Embedded Systems.

Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

5G-and-Beyond Scalable Machines.

Gerhard P. Fettweis, Emil Matús, Robert Wittig, Mattis Hasler, Stefan A. Damjancevic, Seungseok Nam, Sebastian Haas

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Access Interval Prediction for Tightly Coupled Memory Systems.

Robert Wittig, Friedrich Pauls, Emil Matús, Gerhard P. Fettweis

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet.

Friedrich Pauls, Robert Wittig, Gerhard P. Fettweis

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

A Hybrid Execution Approach to Improve the Performance of Dataflow Applications.

Mattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis

Proceedings of the 2019 International SoC Design Conference, 2019

General Multicarrier Modulation Hardware Accelerator for the Internet of Things.

Robert Wittig, Stefan A. Damjancevic, Emil Matús, Gerhard P. Fettweis

Proceedings of the 2019 IEEE Global Communications Conference, 2019

Queue Based Memory Management Unit for Heterogeneous MPSoCs.

Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Statistical Access Interval Prediction for Tightly Coupled Memory Systems.

Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel.

Gerhard P. Fettweis, Mattis Hasler, Robert Wittig, Emil Matús, Stefan A. Damjancevic, Sebastian Haas, Friedrich Pauls, Seungseok Nam, Nairuhi Grigoryan

Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018

An Improved Cellular Nonlinear Network Architecture for Binary and Grayscale Image Processing.

Jens Müller, Robert Wittig, Jan Müller, Ronald Tetzlaff

IEEE Trans. Circuits Syst. II Express Briefs, 2018