Vili Viitamäki

According to our database, Vili Viitamäki authored at least 6 papers between 2017 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

Live Demonstration: 4K100p HEVC Intra Encoder.

Vili Viitamäki, Panu Sjövall, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

FPGA-Powered 4K120p HEVC Intra Encoder.

Panu Sjövall, Vili Viitamäki, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Feasibility of FPGA Accelerated IPsec on Cloud.

Markku Vajaranta, Vili Viitamäki, Arto Oinonen, Timo D. Hämäläinen, Ari Kulmala, Jouni Markunmäki

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server.

Panu Sjovall, Vili Viitamäki, Arto Oinonen, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA.

Vili Viitamäki, Panu Sjovall, Jarno Vanne, Timo D. Hämäläinen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA.

Panu Sjovall, Vili Viitamäki, Jarno Vanne, Timo D. Hämäläinen

Proceedings of the 2017 IEEE International Conference on Acoustics, 2017