Panu Sjövall

According to our database, Panu Sjövall authored at least 15 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Feasibility Study of High-Level Synthesis: Implementation of a Real-Time HEVC Intra Encoder on FPGA.

Panu Sjövall

PhD thesis, 2023

FPGA-Accelerated HEVC Encoder for Energy-Efficient Multi-Access Edge Computing.

Panu Sjövall, Alexandre Mercat, Jarno Vanne

Proceedings of the IEEE International Conference on Image Processing, 2023

2022

High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications.

Panu Sjövall, Ari Lemmetti, Jarno Vanne, Sakari Lahti, Timo D. Hämäläinen

ACM Trans. Design Autom. Electr. Syst., 2022

2021

High-Level Synthesis Implementation of an Accurate HEVC Interpolation Filter on an FPGA.

Panu Sjövall, Matti Rasinen, Ari Lemmetti, Jarno Vanne

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding.

Tero Partanen, Ari Lemmetti, Panu Sjövall, Jarno Vanne

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2019

Are We There Yet? A Study on the State of High-Level Synthesis.

Sakari Lahti, Panu Sjovall, Jarno Vanne, Timo D. Hämäläinen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Visualization of Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud.

Panu Sjövall, Mikko Teuho, Arto Oinonen, Jarno Vanne, Timo D. Hämäläinen

Proceedings of the 2019 IEEE Visual Communications and Image Processing, 2019

Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud.

Panu Sjövall, Arto Oinonen, Mikko Teuho, Jarno Vanne, Timo D. Hämäläinen

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

2018

Live Demonstration: 4K100p HEVC Intra Encoder.

Vili Viitamäki, Panu Sjövall, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

FPGA-Powered 4K120p HEVC Intra Encoder.

Panu Sjövall, Vili Viitamäki, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server.

Panu Sjovall, Vili Viitamäki, Arto Oinonen, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA.

Vili Viitamäki, Panu Sjovall, Jarno Vanne, Timo D. Hämäläinen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA.

Panu Sjovall, Vili Viitamäki, Jarno Vanne, Timo D. Hämäläinen

Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

2016

Distributed systemc simulation on manycore servers.

Janne Virtanen, Panu Sjovall, Marko Viitanen, Timo D. Hämäläinen, Jarno Vanne

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

2015

High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA.

Panu Sjovall, Janne Virtanen, Jarno Vanne, Timo D. Hämäläinen

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015