Vinay Bhaskar Chandratre

According to our database1, Vinay Bhaskar Chandratre authored at least 4 papers between 2008 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2011
Extraction of Aspect Ratio for Non-Manhattan CMOS Devices.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti".
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2008
0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008


  Loading...