Vinay Chenna
Orcid: 0009-0001-4946-1743
According to our database1,
Vinay Chenna authored at least 5 papers
between 2025 and 2026.
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Bibliography
2026
IEEE J. Solid State Circuits, May, 2026
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
13.4 An Inverse-Designed Passively Coupled N-Path Filter with gm-Boosted Active HBT Switches.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
A Blocker-Tolerant Receiver With VCO-Based Non-Uniform Multi-Level Time-Approximation Filter.
IEEE J. Solid State Circuits, December, 2025
11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025