Vinay Chenna

Orcid: 0009-0001-4946-1743

According to our database1, Vinay Chenna authored at least 5 papers between 2025 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Inverse Design of Multilayered Pixelated mm-Wave Power Amplifiers.
IEEE J. Solid State Circuits, May, 2026

A Nonintuitively Frequency-Staggered Wideband mm-Wave Low-Noise Amplifier.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

13.4 An Inverse-Designed Passively Coupled N-Path Filter with gm-Boosted Active HBT Switches.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025
A Blocker-Tolerant Receiver With VCO-Based Non-Uniform Multi-Level Time-Approximation Filter.
IEEE J. Solid State Circuits, December, 2025

11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025


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