Mike Shuo-Wei Chen

Orcid: 0000-0001-7033-272X

Affiliations:
  • University of Southern California, USA
  • University of California, Berkeley, USA


According to our database1, Mike Shuo-Wei Chen authored at least 81 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2024
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration.
IEEE J. Solid State Circuits, January, 2024

Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, January, 2024

5.3 A 0.072mm<sup>2</sup> 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter.
IEEE J. Solid State Circuits, May, 2023

A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration.
IEEE J. Solid State Circuits, 2022

SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter.
IEEE J. Solid State Circuits, 2022

A 10-GS/s 8-bit 2850-μm<sup>2</sup> Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC.
IEEE J. Solid State Circuits, 2022

Non-Uniform Sampling Data Converters: A Journey to Uncharted Circuits and Systems.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

A 10GS/s 8b 25fJ/c-s 2850um<sup>2</sup> Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2021

A Time-Approximation Filter for Direct RF Transmitter.
IEEE J. Solid State Circuits, 2021

26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer.
IEEE J. Solid State Circuits, 2020

16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier.
IEEE J. Solid State Circuits, 2019

A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement.
IEEE J. Solid State Circuits, 2019

A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing.
IEEE J. Solid State Circuits, 2019

A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands.
IEEE J. Solid State Circuits, 2018

A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation.
IEEE J. Solid State Circuits, 2018

A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 200MHz-BW 0.13mm<sup>2</sup> 62dB-DR VCO-based non-uniform sampling ADC with phase-domain level crossing in 65nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

Evolutions of SAR ADC: From high resolution to high speed regime.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter.
IEEE J. Solid State Circuits, 2017

A time multiplexed network architecture for large-scale neuromorphic computing.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016

A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016

A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band.
IEEE J. Solid State Circuits, 2015

A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Cross-Layer Modeling and Simulation of Circuit Reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Overhead minimization techniques for digital phase-locked loop frequency synthesizer.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A non-uniform sampling ADC architecture with embedded alias-free asynchronous filter.
Proceedings of the 2012 IEEE Global Communications Conference, 2012

2011

2010
A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC.
IEEE J. Solid State Circuits, 2010

A calibration-free 800MHz fractional-N digital PLL with embedded TDC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Design and implementation of a CMO 802.11n SoC.
IEEE Commun. Mag., 2009

2008
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN.
IEEE J. Solid State Circuits, 2008


2007
A Subsampling Radio Architecture for Ultrawideband Communications.
IEEE Trans. Signal Process., 2007

Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications.
Proceedings of IEEE International Conference on Communications, 2007

2006
A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS.
IEEE J. Solid State Circuits, 2006

Novel Radio Architectures for UWB, 60 GHz, and Cognitive Wireless Systems.
EURASIP J. Wirel. Commun. Netw., 2006

A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Digital Complex Signal Processing Techniques for Impulse Radio.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling.
IEICE Trans. Electron., 2005

Future wireless systems: UWB, 60GHz, and cognitive radios.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A subsampling UWB radio architecture by analytic signaling.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004


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