Vinita Vasudevan

According to our database1, Vinita Vasudevan authored at least 30 papers between 1997 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Sparse Artificial Neural Networks Using a Novel Smoothed LASSO Penalization.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Fast Proper Orthogonal Decomposition Using Improved Sampling and Iterative Techniques for Singular Value Decomposition.
CoRR, 2019

2018
Probabilistic Error Modeling for Two-part Segmented Approximate Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Optimizing power-accuracy trade-off in approximate adders.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Hierarchical Technique for Statistical Path Selection and Criticality Computation.
ACM Trans. Design Autom. Electr. Syst., 2017

A Hierarchical Singular Value Decomposition Algorithm for Low Rank Matrices.
CoRR, 2017

2016
A Skew-Normal Canonical Model for Statistical Static Timing Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient.
ACM Trans. Design Autom. Electr. Syst., 2016

2015
An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form.
Proceedings of the 52nd Annual Design Automation Conference, 2015

An efficient algorithm for statistical timing yield optimization.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Statistical Criticality Computation Using the Circuit Delay.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2009
Analysis of Clock Jitter in Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2006
Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Scheduling divisible loads on partially reconfigurable hardware.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005
A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Hardware-software co-simulation of bus-based reconfigurable systems.
Microprocess. Microsystems, 2005

2004
Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A time-domain technique for computation of noise-spectral density in linear and nonlinear time-varying circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs.
J. Electron. Test., 2004

A Built-in-Self-Test Scheme for Digital to Analog Converters.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A time-domain technique for computation of noise spectral density in switched capacitor circuits.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique.
Proceedings of the 40th Design Automation Conference, 2003

2000
Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A Transistor Level Placement Tool for Custom Cell Generation.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1998
Symbolic Analysis of Analog Integrated Circuits.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997
Synthesis of Analog CMOS Circuits.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997


  Loading...