Vipin Singh

Orcid: 0009-0008-8924-0970

Affiliations:

National Institute of Technology Jote, Integrated Circuit System Lab, India
Indian Institute of Technology Delhi, Department of Electrical Engineering, New Delhi, India (former)

According to our database¹, Vipin Singh authored at least 6 papers between 2023 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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Bibliography

2025

A Control for Preventing False Tripping of Grid-Tied Renewable Systems With Increased Solar Penetration and Fluctuating Load Demand.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., April, 2025

Soft-Start Header Power Gating for Inrush Alleviated Current Profile.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2025

2024

A Method of Variable Frequency Clock Generation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2024

2023

Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference Radioelektronika, 2023

A Dual Output Bridgeless Rectifier Fed SRM Drive with Improved Power Quality.

[BibT_eX]

[DOI]

Vipin Kumar Singh

Bhim Singh

Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023

αβ-MDSC-MFLL Control with Positive Sequence Extraction and DC Offset Rejection for a Grid-Tied Solar PV-BES Based Power Conversion System.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023

Vipin Singh

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