Pritam Bhattacharjee

According to our database, Pritam Bhattacharjee authored at least 12 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile.

Pritam Bhattacharjee, Alak Majumder

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS.

Pritam Bhattacharjee, G. Naveen Goud, Vipin K. Singh, Vijay P. Yadav, Abir J. Mondal, Alak Majumder

Proceedings of the 33rd International Conference Radioelektronika, 2023

2022

Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC.

Pritam Bhattacharjee, Prerna Rana, Bidyut K. Bhattacharyya, Alak Majumder

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time.

Pritam Bhattacharjee, Bidyut K. Bhattacharyya, Alak Majumder

Circuits Syst. Signal Process., 2021

2019

A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application.

Pritam Bhattacharjee, Alak Majumder

J. Circuits Syst. Comput., 2019

2018

A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips.

Alak Majumder, Pritam Bhattacharjee, Tushar Dhabal Das

J. Circuits Syst. Comput., 2018

Data-Dependent Clock Gating approach for Low Power Sequential System.

Dhiraj Sarkar, Pritam Bhattacharjee, Alak Majumder

CoRR, 2018

LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications.

Pritam Bhattacharjee, Bipasha Nath, Alak Majumder

CoRR, 2018

2017

Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell.

Pritam Bhattacharjee, Kunal Das, Arijit Dey, Debashis De, Swarnendu Kumar Chakraborty

J. Low Power Electron., 2017

Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip.

Alak Majumder, Pritam Bhattacharjee

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016

A 90 nm leakage control transistor based clock gating for low power flip flop applications.

Pritam Bhattacharjee, Alak Majumder, Tushar Dhabal Das

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder.

Pritam Bhattacharjee, Alak Majumder

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016