Vishesh Dokania

Orcid: 0000-0003-0000-3052

According to our database¹, Vishesh Dokania authored at least 1 paper in 2015.

Collaborative distances:

Dijkstra number² of six.
Erdős number³ of five.

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Bibliography

2015

Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells.

[BibT_eX]

[DOI]

Vishesh Dokania

Aminul Islam

IET Circuits Devices Syst., 2015

Vishesh Dokania

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