Vishesh Dokania

Orcid: 0000-0003-0000-3052

According to our database1, Vishesh Dokania authored at least 1 paper in 2015.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2015
Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells.
IET Circuits Devices Syst., 2015


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