Vrajesh Patel

Orcid: 0000-0003-0781-5475

According to our database1, Vrajesh Patel authored at least 3 papers between 2023 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023


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