Weichong Chen

Orcid: 0000-0001-7804-6605

According to our database¹, Weichong Chen authored at least 9 papers between 2022 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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Bibliography

2026

HARD: A Heterogeneous Last-Level Cache Architecture With Readless Hierarchical Tag and Dynamic-LRU Policy.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2026

2025

Low-Power and Low-Cost AI Processor With Distributed-Aggregated Classification Architecture for Wearable Epilepsy Seizure Detection.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., February, 2025

UIC: A unified and scalable chip integrating neuromorphic computation and general purpose processor.

[BibT_eX]

[DOI]

Microelectron. J., 2025

FDAIMC: A Fully-Differential Analog In-Memory-Computing for MAC in MRAM with Accuracy Calibration Under Process and Voltage Variation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

2023

Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

Computing Resistance-Style Image Sensors for Artificial Neural Networks.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2023

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2023

2022

An in-memory computing multiply-and-accumulate circuit based on ternary STT-MRAMs for convolutional neural networks.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

Weichong Chen

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Bibliography

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