Weihao Jie

According to our database, Weihao Jie authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoM_REF of -247.9 dB at 3 GHz With a Ring Oscillator.

Tong Zhang, Yiwen Zhang, Xueke Cai, Weihao Jie, Yanling Zheng, Deyong Li, Yang Zhao, Yongfu Li, Honglan Jiang, Patrick P. Mercier, Hui Wang

IEEE J. Solid State Circuits, March, 2026

A 28-Gbps 28-nm CMOS Wireline Receiver Analog Front End With An Adaptive CTLE Enabled By A Hexagonal Mask Eye-Opening Monitor.

Yixing Jiang, Runtao Huo, Weihao Jie, Yan Liu, Minmin You, Jingquan Liu, Hui Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025

4.2 A 1.8-to-3.0GHz Fully Integrated All-In-One CMOS Frequency Management Module Achieving -47/+42ppm Inaccuracy from -40 to 95°C and -150/+70ppm After Accelerated Aging.

Runtao Huo, Tong Zhang, Weihao Jie, Yanling Zheng, Deyong Li, Li Gao, Yang Zhao, Honglan Jiang, Yongfu Li, Patrick P. Mercier, Hui Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of -247.9dB at 3GHz with a Ring Oscillator.

Xueke Cai, Tong Zhang, Weihao Jie, Yanling Zheng, Deyong Li, Yiwen Zhang, Yang Zhao, Yongfu Li, Honglan Jiang, Patrick P. Mercier, Hui Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025