Wen-Yi Chen

According to our database1, Wen-Yi Chen authored at least 15 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

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Bibliography

2023
The Impact of Character Color Combinations on Legibility When Presented on Optical Head-Mounted Displays During Walking.
Proceedings of the IEEE International Conference on Industrial Engineering and Engineering Management, 2023

A Novel Ciphertext-Policy Attribute-Based Encryption Supporting Dual Membership.
Proceedings of the 18th Asia Joint Conference on Information Security, 2023

2022
On the Relationships among Nurse Staffing, Inpatient Care Quality, and Hospital Competition under the Global Budget Payment Scheme of Taiwan's National Health Insurance System: Mixed Frequency VAR Analyses.
Syst., 2022

2019
Multipath Transmission Mechanism with P4 Switches in Software Defined Networks.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

2016
TRINPON: A novel network architecture for supporting private networking capability over LR EPONs.
Proceedings of the 2016 International Conference on Information Networking, 2016

2015
Chinese Spelling Checker Based on an Inverted Index List with a Rescoring Mechanism.
ACM Trans. Asian Low Resour. Lang. Inf. Process., 2015

2013
Chinese Word Spelling Correction Based on N-gram Ranked Inverted Index List.
Proceedings of the Seventh SIGHAN Workshop on Chinese Language Processing, 2013

2011
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs.
IEEE J. Solid State Circuits, 2011

2010
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2006
Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004
Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004


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