William Tatinian

According to our database1, William Tatinian authored at least 15 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Design and modeling of heterogeneous semi-active wake-up radio for sensor network applications.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022
Hierarchical Modeling of 868MHz Wake-up Radio in OMNeT++.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2012
Ultra-Low-Power Audio Communication System for Cochlear Implant Application.
J. Low Power Electron., 2012


2011
Ultra-Low-Power Radio Microphone for Cochlear Implant Application.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

2010
Battery lifetime modelling for a 2.45GHz cochlear implant application.
Proceedings of the 2010 IEEE International Behavioral Modeling and Simulation Conference, 2010

BER and power consumption estimation based on hierarchical modeling of a 2.4 GHz power amplifier.
Proceedings of the 2010 IEEE International Behavioral Modeling and Simulation Conference, 2010

2009
On the use of behavioral modeling within the RFIC design flow: Satellite receiver case study.
Microelectron. J., 2009

Evaluation of SystemC-AMS modeling capabilities of RF front-end non-linearities: satellite receiver case study.
Proceedings of the Forum on specification and Design Languages, 2009

2008
Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology.
Microelectron. J., 2008

Application of Bottom-Up Methodology to RTW VCO.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007
System-Design-Oriented Low Noise Amplifier Modeling.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Hierarchical Modeling of a Fractional Phase Locked Loop.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Scalable Model for Multi-Standard Phase Locked Loop.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
VHDL-AMS modeling of a multi-standard phase locked loop.
Proceedings of the 12th IEEE International Conference on Electronics, 2005


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