Michel Auguin

According to our database1, Michel Auguin authored at least 88 papers between 1982 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Mobile Terminals System-Level Memory Exploratio for Power and Performance Optimization.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Towards a Multi-mission QoS and Energy Manager for Autonomous Mobile Robots.
Proceedings of the Second IEEE International Conference on Robotic Computing, 2018

2017
Power and performance aware electronic system level design.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

A framework for system level low power design space exploration.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
An ESL framework for low power architecture design space exploration.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Application and OS unconscious power manager for SoC systems.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A methodology for inserting clock-management strategies in transaction-level models of systemon- chips.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015

SOC Power Management Strategy Based on Global Hardware Functional State Analysis.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
A Joint Duty-Cycle and Transmission Power Management for Energy Harvesting WSN.
IEEE Trans. Industrial Informatics, 2014

AUTSEG: Automatic Test Set Generator for Embedded Reactive Systems.
Proceedings of the Testing Software and Systems, 2014

2013
A multichannel design for QoS aware energy efficient clustering and routing in WMSN.
IJSNet, 2013

Power domain management interface: flexible protocol interface for transaction-level power domain management.
IET Computers & Digital Techniques, 2013

Power-Aware Wrappers for Transaction-Level Virtual Prototypes: A Black Box Based Approach.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Temperature-aware DVFS-DPM for real-time applications under variable ambient temperature.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013

Mobility Management Approach for IEEE802.15.4/ZigBee Nodes in a Noisy Environment.
Proceedings of the ARCS 2013, 2013

2012
Waveperf: a benchmark generator for performance evaluation.
SIGBED Review, 2012

Using unified power format standard concepts for power-aware design and verification of systems-onchip at transaction level.
IET Circuits, Devices & Systems, 2012

A framework for modeling and simulating energy harvesting WSN nodes with efficient power management policies.
EURASIP J. Emb. Sys., 2012

Using model driven engineering to reliably accelerate early Low Power Intent Exploration for a system-on-chip design.
Proceedings of the ACM Symposium on Applied Computing, 2012

A semi-partitioned real-time scheduling approach for periodic task systems on multicore platforms.
Proceedings of the ACM Symposium on Applied Computing, 2012

An Open-Loop Energy Neutral Power Manager for Solar Harvesting WSN.
Proceedings of the PECCS 2012, 2012

A high level mixed hardware/software modeling framework for rapid performance estimation.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

An Efficient Mobility Management Approach for IEEE 802.15.4/ZigBee Nodes.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Black-box and white-box early power intent simulation and verification: Two novel approaches.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

GRECO: GREen communicating objects.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Hybrid power management in real time embedded systems: an interplay of DVFS and DPM techniques.
Real-Time Systems, 2011

Two-level Hierarchical Scheduling Algorithm for Real-time Multiprocessor Systems.
JSW, 2011

A performance estimation flow for embedded systems with mixed software/hardware modeling.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Energy Efficient Multi Channel Design for ClusteredWireless Sensor Networks.
Proceedings of the ARCS 2011, 2011

2010
Implantation d'un décodeur H.264 sur plateforme multiprocesseur avec gestion énergétique.
Technique et Science Informatiques, 2010

Energy Efficient Data Reporting Techniques for Grid Based Wireless Sensor Networks.
JNW, 2010

Cross layer design for QoS aware energy efficient data reporting in WSN.
Proceedings of the 2010 7th International Symposium on Wireless Communication Systems, 2010

Power Management in Real Time Embedded Systems through Online and Adaptive Interplay of DPM and DVFS Policies.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

Power Consumption Modeling for DVFS Exploitation.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Wireless Sensor Network node global energy consumption modeling.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

An inter-task real time DVFS scheme for multiprocessor embedded systems.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

Dynamic Data Dissemination Technique for WSN.
Proceedings of the ARCS '10, 2010

2009
UML for Modelling and Performance Estimation of Embedded Systems.
Journal of Object Technology, 2009

UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs).
Journal of Object Technology, 2009

Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Analytical Model for Energy Consumption Analysis in Grid Based Wireless Sensor Networks.
Proceedings of the NTMS 2009, 2009

A framework for offline optimization of energy consumption in real time multiprocessor system-on-chip.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Low Power Main Memory Configuration and Tasks Allocation.
J. Low Power Electronics, 2008

Weight Bound Limits in Supertasking Approach for Guaranteed Timeline Constraints.
Proceedings of the 37th International Conference on Parallel Processing, 2008

Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Optimisation de la consommation mémoire multibanc pour un système multitâche.
Technique et Science Informatiques, 2007

Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures.
Trans. HiPEAC, 2007

2006
EPICURE: A partitioning and co-design framework for reconfigurable computing.
Microprocessors and Microsystems, 2006

Main Memory Energy Optimization for Multi-Task Applications.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Scheduler-based Multi-Bank Main Memory Configuration for Energy Reduction.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

FPGA-based generic neural network architecture.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

Energy Optimization of a Multi-bank Main Memory.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Contentions-conscious dynamic but deterministic scheduling of computational and communication tasks.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

System Level Multi-bank Main Memory Configuration for Energy Reduction.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Multi-Bank Memory Allocation for Multimedia Application.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy Optimization.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

An efficient on-line Approach for on-chip HW/SW partitioner and scheduler.
Proceedings of the ARCS 2006, 2006

2005
Energy aware memory architecture configuration.
SIGARCH Computer Architecture News, 2005

An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

A SW/Configware Codesign Methodology for Control Dominated Applications.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2003
Partitionnement logiciel matériel ciblant une architecture reconfigurable dynamiquement.
Technique et Science Informatiques, 2003

Partitioning Reactive Data Flow Applications On Dynamically Reconfigurable Systems.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Energy Optimization in a HW/SW Tool: Design of Low.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

2002
Partitionnement de spécifications flots de données conditionnels pour la conception de systèmes embarqués.
Technique et Science Informatiques, 2002

Architecture and application partitioning for reconfigurable system design.
Proceedings of the 11th European Signal Processing Conference, 2002

HW / SW partitioning approach for reconfigurable system design.
Proceedings of the International Conference on Compilers, 2002

2001
Power Consumption Model for the DSP OAK Processor.
Proceedings of the SOC Design Methodologies, 2001

CODEF: a system level design space exploration tool.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
A codesign back-end approach for embedded system design.
ACM Trans. Design Autom. Electr. Syst., 2000

Partitioning Conditional Data Flow Graphs for Embedded System Design.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
A Prototyping Method of Embedded Real Time Systems for Signal Processing Applications.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Rapid Development of Optimized DSP Code from a High Level Description Through Software Estimations.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Improving "performance vs silicon size" tradeoffs using coprocessors: A case study: G.721 on OAK and Pine DSP Cores.
Proceedings of the 9th European Signal Processing Conference, 1998

Communication synthesis and HW/SW integration for embedded system design.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

A path analysis based partitioning for time constrained embedded systems.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
A codesign experiment in acoustic echo cancellation GMDF.
ACM Trans. Design Autom. Electr. Syst., 1997

A generic multi-unit architecture for codesign methodologies.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
A Codesign Experiment in Acoustic Echo Cancellation: GMDFa.
Proceedings of the 9th International Symposium on System Synthesis, 1996

1994
Automatic exploration of VLIW processor architectures from a designer's experience based specification.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

Towards a multi-formalism framework for architectural synthesis: the ASAR project.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
OPSILA: A Vector and Parallel Processor.
IEEE Trans. Computers, 1993

Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures.
Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993

1992
A comparison study of minimization methods of unit interconnection in VLIW processors.
Microprocessing and Microprogramming, 1992

A partitioning algorithm for system-level synthesis.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1990
Component Labeling on SIMD-SPMD Architecture.
Proceedings of IAPR Workshop on Machine Vision Applications, 1990

1988
Image processing on a SIMD/SPMD architecture: OPSILA.
Proceedings of the 9th International Conference on Pattern Recognition, 1988

1982
Efficient multiprocessor architecture for digital signal processing.
Proceedings of the IEEE International Conference on Acoustics, 1982


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