Xiang Ling

Orcid: 0000-0002-2012-8795

Affiliations:
  • University of Electronic Science and Technology of China, Chengdu, China


According to our database1, Xiang Ling authored at least 17 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Deep Reinforcement Learning-Based Anti-Jamming Algorithm Using Dual Action Network.
IEEE Trans. Wirel. Commun., July, 2023

A scheduling algorithm for heterogeneous computing systems by edge cover queue.
Knowl. Based Syst., April, 2023

Hierarchical multi-beam training with the presence of the sub-connected hybrid beamforming architecture.
Trans. Emerg. Telecommun. Technol., March, 2023

2019
Nonlinear Complex Support Vector Regression for Fading Channel Estimation in FBMC-OQAM System.
IEEE Wirel. Commun. Lett., 2019

Novel RAPF scheme and its performance of PAPR reduction and BER in FBMC-OQAM system.
IET Commun., 2019

Compressive Sensing-Based Channel Estimation for FBMC-OQAM System Under Doubly Selective Channels.
IEEE Access, 2019

Multi-applications mapping platform based on hardware and software.
Proceedings of the 3rd International Conference on High Performance Compilation, 2019

2018
Low-Complexity PTS Scheme for PAPR Reduction in FBMC-OQAM Systems.
IEEE Commun. Lett., 2018

2017
多核阵列的任务调度技术研究 (New Task Scheduling Technique for Multicore Arrays).
计算机科学, 2017

2015
MACRON: The NoC-Based Many-Core Parallel Processing Platform and Its Applications in 4G Communication Systems.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

A dynamic and low latency wireless NoC architecture.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2012
A novel 3D NoC architecture based on De Bruijn graph.
Comput. Electr. Eng., 2012

2011
A Cooperative Transmission and Receiving Scheme for IDMA with Time-Reversal Technique.
Wirel. Pers. Commun., 2011

2010
A 2<sup><i>n</i></sup> scaling scheme for signed RNS integers and its VLSI implementation.
Sci. China Inf. Sci., 2010

Energy and delay-aware mapping for real-time digital processing system on network on chip platforms.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2008
An efficient RNS parity checker for moduli set {2<sup> <i>n</i></sup> - 1, 2<sup> <i>n</i> </sup> + 1, 2<sup>2 <i>n</i> </sup> + 1} and its applications.
Sci. China Ser. F Inf. Sci., 2008

HW/SW co-simulation platforms for VLSI design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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