Xiaoheng Chen

According to our database1, Xiaoheng Chen authored at least 10 papers between 2009 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2013
A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes.
IEEE Trans. Commun., 2013

2012
High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Exploiting the shift property of structured LDPC codes for reduced-complexity sliced message passing based decoder design.
Proceedings of the International Conference on Computing, Networking and Communications, 2012

2011
Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA.
ACM Trans. Reconfigurable Technol. Syst., 2011

Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing.
Proceedings of the Design, Automation and Test in Europe, 2009

FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes.
Proceedings of the 47th Annual Allerton Conference on Communication, 2009


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